Semiconductor memory device having main word decoder skipping defective address during sequential access and method of controlling thereof
AssigneeNEC Corporation
InventorTadahiko Sugibayashi
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Abstract
A semiconductor memory device has a main word decoder for selecting a cluster from a memory cell block, and the main word decoder stores pieces of control data information each representative of whether the cluster is defective or non-defective; while an external device is sequentially accessing the clusters, the main word decoder skips the defective clusters on the basis of the piece of control data information, and accelerates the data access to the clusters.
Claims8
A semiconductor memory device for skipping defective word lines, comprising:
- defective word line discriminating means respectively incorporated in row decoders for producing binary signals representative of said defective word lines;
- and
- converting means responsive to said binary signals for converting external logical addresses assigned to non-defective word lines to addresses lower than said external logical addresses.
A semiconductor memory device comprising
- a plurality of memory cells divided into a plurality of memory cell groups respectively assigned physical addresses, at least one defective memory cell group being incorporated in said plurality of memory cell groups,
- a decoder including a plurality of decoder units respectively corresponding to said plurality of memory cell groups, and including
- a plurality of memory units respectively storing control data information each representative of whether the associated memory cell group is defective or non-defective and producing first control signals representative of said control data information, respectively,
- a plurality of driver units respectively connected to said plurality of memory cell groups and responsive to second control signals for making non-defective memory cell groups accessible, and
- an address converter connected between said plurality of memory units and said plurality of driver units, responsive to a third control signal for converting external logical addresses indicative of said non-defective memory cell groups to said physical addresses assigned to said non-defective memory cell groups specified by said first control signals and selectively supplying said second control signals to said plurality of driver units, and
- a decoder controller supplying said third control signal to said address converter.
A method for controlling a semiconductor memory device having a plurality of memory cell groups respectively assigned physical addresses, comprising the steps of:
- a) counting defective memory cell groups of said plurality of memory cell groups after said semiconductor memory device is powered;
- b) determining the maximum logical address assigned to one of non-defective memory cell groups of said plurality of memory cell groups on the basis of the number of defective memory cell groups;
- c) supplying control data information representative of said maximum logical address to the outside of said semiconductor memory device;
- and
- d) entering into a standard mode where an external device selectively accesses said non-defective memory cell groups with a logical address.
Dependencies are inferred from the claim text.