Memory-row selector having a test function
AssigneeSTMicroelectronics S.r.l.
InventorDavid C. McClure
Life of this patent
Estimating the term…
Abstract
A memory-row selector includes an address input terminal, a mode terminal, and even-row-select and odd-row-select terminals. While a test signal level occupies the mode terminal (ie., during a test mode), the selector places either an active level or an inactive level on both of the even-row-select and odd-row-select terminals. An active level on both of the select terminals enables both even-row and odd-row word lines, and allows writing to or reading from memory cells in both odd and even rows. An inactive level on both of the select terminals disables both even-row and odd-row word lines, including the word line coupled to the addressed memory cell.
Claims12
A memory device, comprising:
- an address decoder;
- an array of memory cells arranged in rows and columns, each column having a bit-true and a bit-complement lines coupled to those of said memory cells in said each column, each row having a word line coupled to those of said memory cells in said each row;
- a read/write circuit coupled to said decoder and to said array, said read/write circuit operable to simultaneously drive first and second test signals respectively onto said bit-true and bit-complement lines of an addressed column during testing of said addressed column;
- and
- a memory-row selector coupled to said address decoder and to said array, said selector having an even-row output terminal and an odd-row output terminal, said selector operable to drive a same logic level onto both of said output terminals during said testing such that those of said word lines coupled to memory cells in said addressed column carry an inactive logic level.
A method, comprising:
- addressing a column of memory cells in a memory array that is arranged in rows and columns, said columns each having a bit-true and a bit-complement lines;
- uncoupling said memory cells from said bit-true and bit-complement lines of said addressed column with a row-selector circuit;
- and
- driving first and second test signals onto said bit-true and bit-complement lines, respectively, while said memory cells are uncoupled from said bit-true and bit-complement lines.
Dependencies are inferred from the claim text.