US 5,848,016 A · Merged Memory and Logic (MML) integrated circuits and methods including serial data path comparing

Abstract

An integrated circuit having a wide internal data path, such as a Merged Memory and Logic (MML) integrated circuit, is tested by serially comparing data on one of the data paths to data on selected others of the data paths. A first indication is provided if the serially compared data on the one of the data paths and on the selected others of the data paths are all a first logic value. A second indication is provided if the serially compared data on the one of the data paths and on the selected others of the data paths are all a second logic value. A third indication is provided if the serially compared data on the one of the data paths and on the selected others of the data paths are of differing logic values. By serially comparing data on one of the data paths to data on selected others of the data paths, a reduced number of comparators may be provided. Efficient circuits and methods for testing integrated circuits, such as memory integrated circuits or logic integrated circuits, may thereby be provided.

Claims27

Dependent claims

A merged memory and logic (MML) integrated circuit comprising:

a memory block;
a logic block;
a plurality of data paths that interconnect the memory block and the logic block;
and
a serial comparing circuit that serially compares data on one of the data paths to data on selected others of the data paths, to provide a first indication if the serially compared data on the one of the data paths and on the selected others of the data paths are all a first logic value, to provide a second indication if the serially compared data on the one of the data paths and on the selected others of the data paths are all a second logic value, and to provide a third indication if the serially compared data on the one of the data paths and on the selected others of the data paths are of differing logic values.

2 more elements

A merged memory and logic (MML) integrated circuit comprising:

memory means;
logic means;
a plurality of data paths that interconnect the memory means and the logic means;
and
means for serially comparing data on one of the data paths to data on selected others of the data paths, to provide a first indication if the serially compared data on the one of the data paths and on the selected others of the data paths are all a first logic value, to provide a second indication if the serially compared data on the one of the data paths and on the selected others of the data paths are all a second logic value, and to provide a third indication if the serially compared data on the one of the data paths and on the selected others of the data paths are of differing logic values.

2 more elements

A method of testing a merged memory and logic (MML) integrated circuit including a memory block, a logic block and a plurality of data paths that interconnect the memory block and the logic block, the testing method comprising the following step that is performed in the MML integrated circuit:

serially comparing data on one of the data paths to data on selected others of the data paths, to provide a first indication if the serially compared data on the one of the data paths and on the selected others of the data paths are all a first logic value, to provide a second indication if the serially compared data on the one of the data paths and on the selected others of the data paths are all a second logic value, and to provide a third indication if the serially compared data on the one of the data paths and on the selected others of the data paths are of differing logic values.

Dependencies are inferred from the claim text.

Merged Memory and Logic (MML) integrated circuits and methods including serial data path comparing

Life of this patent

Merged Memory and Logic (MML) integrated circuits and methods including serial data path comparing

Life of this patent

Abstract

Claims27