Semiconductor device such as a static random access memory (SRAM) having a low power mode using a clock disable circuit

A static random access memory (SRAM) device having a reduced power mode comprising:

• means for outputting a disable signal responsive to a reduced power command signal applied to said device asynchronously relative to an external clock signal;
• means for generating an internal clock signal configured to discontinue said internal clock signal in response to said disable signal, and;
• at least one chip enable register for deselecting said device in a predetermined fashion;
• wherein said means for outputting said disable signal maintains said internal clock signal for at least one clock pulse after said reduced power command signal is applied to said device, and said at least one internal clock pulse is operative to clock a non-active chip enable signal into said at least one chip enable register to thereby obviate the need to deselect said device prior to applying said reduced power command signal.

A semiconductor device having a reduced power mode comprising:

• a control circuit having an input terminal configured to receive a command signal and generate a disable signal in response thereto;
• and,
• an internal clock generator having (i) an input terminal configured to receive an external clock signal, (ii) an output terminal configured to output an internal clock signal and (iii) an enable terminal configured to discontinue said internal clock signal in response to said disable signal;
• said control circuit including a pipeline register configured to control generation of said disable signal such that said internal clock signal is maintained for at least one clock pulse after said command signal is received by said control circuit.

A method of operating a semiconductor device comprising the steps of:

• (A) generating an internal clock signal having a plurality of pulses in response to an external clock signal;
• (B) instructing said device to reduce power consumption;
• (C) generating at least one further internal clock pulse after said instructing step;
• and,
• (D) discontinuing said internal clock signal thereafter.

A semiconductor device having a reduced power mode comprising:

• means for outputting a disable signal responsive to a reduced power command signal;
• and,
• means for generating an internal clock signal configured to discontinue said internal clock signal in response to said disable signal, said internal clock signal generating means including (i) a clock buffer circuit and (ii) a clock signal generator, said clock buffer circuit having:
• a NOR gate with a first input terminal, a second input terminal, and an output terminal wherein said NOR gate first input terminal is configured to receive said external clock signal, and said NOR gate second input terminal is configured to receive a true stopclock signal;
• and,
• an INVERTER gate having an input terminal and an output terminal wherein said INVERTER gate input terminal is coupled to said NOR gate output terminal, said INVERTER gate output terminal being configured to generate a buffered external clock signal;
• wherein said means for outputting said disable signal maintains said internal clock signal for at least one clock pulse after said reduced power command signal is applied to said device.