Row decoding circuit for semiconductor non-volatile electrically programmable memory and corresponding method

A row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of a type having a matrix of memory cells laid out as cell rows and columns, the matrix being divided into sectors such that each sector has a corresponding plurality of rows, the row decoding circuit comprising:

• an input stage that receives input row decode signals and the supply voltages;
• and
• an output stage that is driven by the input row decode signals and supply voltages, the output stage having:
• a complementary pair of high-voltage MOS transistors including a pull-up transistor and a pull-down transistor, wherein the pull-up and pull-down transistors are connected to form an output terminal, wherein the output terminal is connected to a plurality of rows corresponding to a sector of the matrix, and
• a MOS transistor of the P-channel depletion type with enhanced gate oxide, wherein the MOS transistor is disposed between the output terminal and the pull-down transistor;
• and
• a voltage generator incorporating a charge pump;
• and
• a switching device including:
• a main switch connected to a supply voltage reference and the voltage generator, and
• a set of local switches connected to the main switch, each local switch being associated with a sector of the matrix.

A row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of a type having a matrix of memory cells laid out as cell rows and columns, the matrix being divided into sectors such that each sector has a corresponding plurality of rows, the row decoding circuit comprising:

• an input stage that receives input row decode signals and the supply voltages;
• and
• an output stage that is driven by the input row decode signals and supply voltages, the output stage having:
• a complementary pair of high-voltage MOS transistors including a pull-up transistor and a pull-down transistor, wherein the pull-up and pull-down transistors are connected to form an output terminal wherein the output terminal is connected to a plurality of rows corresponding to a sector of the matrix, and
• a MOS transistor of the P-channel depletion tape with enhanced gate oxide, wherein the MOS transistor is disposed between the output terminal and the pull-down transistor;
• and
• a voltage regulator effective to produce a drive voltage for driving a control terminal of the pull-up transistor, the regulator including:
• a current generator formed of a set of high-voltage P-channel MOS transistors connected to one another to form at least one current mirror, and
• a series of enable transistors adapted to receive actuation signals on their control terminals.

A row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of a type having a matrix of memory cells laid out as cell rows and columns, the matrix being divided into sectors such that each sector has a corresponding plurality of rows, the row decoding circuit comprising:

• an input stage that receives input row decode signals and the supply voltages;
• and
• an output stage that is driven by the input row decode signals and supply voltages, the output stage having:
• a complementary pair of high-voltage MOS transistors including a pull-up transistor and a pull-down transistor, wherein the pull-up and pull-down transistors are connected to form an output terminal, wherein the output terminal is connected to a plurality of rows corresponding to a sector of the matrix, and
• a MOS transistor of the P-channel depletion type with enhanced gate oxide, wherein the MOS transistor is disposed between the output terminal and the pull-down transistor;
• and
• at the end of each row, a row diode having a first end connected to the end of the row, and a second end connected to a node adapted to receive a negative voltage from a negative charge pump.