Semiconductor memory device having hierarchical bit line structure employing improved bit line precharging system

A semiconductor memory device comprising:

• a semiconductor substrate;
• a plurality of memory cell blocks arranged on said semiconductor substrate in a row direction;
• a plurality of main bit line pairs arranged on said semiconductor substrate across said plurality of memory blocks;
• and
• precharging potential generation means generating a prescribed precharging potential,
• wherein each of said plurality of memory cell blocks includes
• a plurality of subbit line pairs corresponding to said plurality of main bit line pairs,
• the subbit lines of each subbit line pair arranged structurally along a single straight line extending in a direction parallel to the corresponding main bit line pair,
• wherein each of said plurality of memory cell blocks further includes
• a plurality of selection transistor pairs, corresponding to said plurality of subbit line pairs and being turned on in response to a prescribed block selection signal, each selection transistor pair connected between the corresponding main bit line pair and the corresponding subbit line pair,
• a plurality of word lines each intersecting one subbit line of each said plurality of subbit line pairs,
• a plurality of memory cells corresponding to intersection points between said word lines and said subbit lines, each memory cell being connected to the corresponding subbit line and the corresponding word line,
• a first precharging potential supply line extending in a direction parallel to said word lines and between the subbit lines of the subbit line pairs and supplied with said precharging potential from said precharging potential generation means,
• a first precharging control line extending in a direction parallel to said word lines and between said first precharging potential supply line and a first plurality of said word lines,
• a second precharging control line extending in a direction parallel to said word lines and between said first precharging potential supply line and a second plurality of said word lines,
• a plurality of first precharging transistors, corresponding to one subbit line of each of said plurality of subbit line pairs and connected between the corresponding one subbit line and said first precharging potential supply line and having a control electrode being connected to said first precharging control line, and
• a plurality of second precharging transistors, corresponding to the other subbit line of each of said plurality of subbit line pairs and connected between the corresponding other subbit line and said first precharging potential supply line and having a control electrode being connected to said second precharging control line.