Circuit and method for antifuse stress test
AssigneeMicron Technology, Inc.
InventorJoseph C. Sher
Life of this patent
Estimating the term…
Abstract
A test circuit for stress testing antifuses before programming. The test circuit provides a voltage to an antifuse detection circuit during antifuse stress testing. In one embodiment, the provided voltage is externally received at a probe pad. In another embodiment, the test circuit controls a voltage generating circuit output voltage from a normal operating voltage to a stress voltage, such as by shifting the ground reference for the voltage generating circuit. The stress voltage can be varied as needed for a particular test setup and/or for different batches of antifuse circuits. Since the stress voltage is independent of the power supply voltage VCC, antifuse stressing can be concurrent with other pre-fuse tests, obviating the need for a dedicated antifuse stress test and reducing test time.
Claims23
A test circuit for providing to a test element an operating voltage, in a normal mode of operation, and a stress voltage, in an stress test mode of operation, the test circuit comprising:
- an output node coupled to the test element;
- a first gating circuit for coupling the output of a voltage source to the output node;
- a second gating circuit for coupling a stress voltage received from an external pad to the output node in response to a stress voltage enable signal.
A test circuit for providing to a test element, an operating voltage, in a normal mode of operation, and a stress voltage, in a stress test mode of operation, the test circuit comprising:
- an output node coupled to the test element;
- a voltage generating circuit for providing an output voltage to the output node;
- and
- a control circuit, responsive to a stress voltage enable signal, for adjusting the output voltage from the operating voltage level to the stress voltage level.
A semiconductor memory device, comprising:
- a memory array having a plurality of addressable memory cells;
- an addressing circuit for accessing the memory cells;
- a plurality of programmable elements associated with the addressing circuit, having a detection circuit for detecting the element's programming state;
- and
- a test circuit for stress testing the element, the test circuit comprising:
- an output node coupled to the element;
- a voltage generating circuit providing an output voltage to the output node;
- and
- a control circuit for controlling the output voltage at the output node between an operating voltage and a stress voltage, based upon a stress voltage enable signal.
A method for stress testing a test element, the method comprising:
- decoupling, from a voltage generating circuit, an output node coupled to the test element;
- coupling the output node to a probe pad;
- and
- applying a stress voltage to the pad.
A method for stress testing a test element, the method comprising:
- coupling an output node to the test element;
- coupling a voltage generating circuit output node to the output node;
- adjusting the voltage generating circuit output node voltage magnitude from an operating voltage to a stress voltage;
- and
- applying the stress voltage to the output node for adjusting a voltage that is applied to the test element.
Dependencies are inferred from the claim text.