Floating bitline test mode with digitally controllable bitline equalizers
AssigneesSiemens Aktiengesellschaft, International Business Machines Corporation
InventorsToshiaki Kirihata, Hing Wong, Bozidar Krsnik
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Abstract
A method for generating a floating bitline test mode using digitally controllable bitline equalizers is provided. The method utilizes digitally controlled dummy timing cycles to detect a leaky bitline during the floating bitline test mode. A negative pulsed TEST signal is generated to cause the bitline equalizers to go low and cause the floating bitline state. The implementation of dummy timing cycles eliminates the need for additional external control of internal timings during a bitline test mode. Upon the termination of the dummy timing cycle, the normal read operation continues without interruption.
Claims11
A method for detecting leaky bitlines in semiconductor memories comprising the steps of:
- generating at least one dummy timing cycle;
- disabling a bitline equalizer to create a floating bitline test mode;
- and
- detecting a defective bitline by reading from the semiconductor memory as in a normal mode.
A method of detecting a leaky bitline in DRAM comprising the steps of:
- disabling a bitline equalizer to create a floating bitline test mode;
- initiating at least one dummy timing cycle at the beginning of the test mode using a VLSI tester, said at least one dummy timing cycle being digitally controllable by said VLSI tester;
- and
- determining the presence of a defective bitline during the at least one dummy timing cycle.
Dependencies are inferred from the claim text.