Redundancy circuit for semiconductor storage apparatus

Abstract

A redundancy circuit for a semiconductor storage apparatus controls replacement of a normal system memory cell by a redundant system memory cell. Each of first and second fuse circuits include fuses provided in correspondence to individual bits of an address signal constituted by a plurality of bits for designating an address of the normal system memory cell, and outputs an output signal of high level or low level in dependence on whether or not the fuse is broken or not. A non-redundancy decision unit decides whether the normal system memory cell is to be used or not on the basis of the output signals of the first and second fuse circuits to thereby output a non-redundancy flag indicating result of the decision. A MOS transistor has a gate terminal applied with the non-redundancy flag and is changed over between a conducting state and a non-conducting state in dependence on the non-redundancy flag. An address decoder for the normal system memory cell decodes the address signal when the MOS transistor is in the conducting state.

Dependencies are inferred from the claim text.