Redundant semiconductor memory device using a single now address decoder for driving both sub-wordlines and redundant sub-wordlines

A memory, comprising:

• a plurality of memory cell blocks;
• a plurality of subword drivers, operatively coupled and corresponding to the plurality of memory cell blocks, for selecting respective subword lines;
• a plurality of drivers, coupled to said subword lines, for providing information to the subword lines, said drivers receiving first and second types of information depending on a normal mode and a redundancy mode of said memory;
• and
• a single, row address decoder, operatively coupled to said plurality of drivers, for selectively providing said first and second types of information to said plurality of drivers.

A memory, comprising:

• at least one main word line;
• at least one redundant main word line arranged in regard to said at least one main word line;
• a first driver, operatively coupled to said at least one main word line, for driving said at least one main word line;
• a second driver, operatively coupled to said at least one redundant main word line, for driving said at least one redundant main word line;
• means, operatively coupled to said first and second drivers, for selectively issuing first and second signals to said first and second drivers depending upon a normal mode and a redundancy mode, respectively;
• a row driver, operatively coupled to both said first and second drivers, for outputting a same output selectively used with each of said first and second drivers, depending upon whether said first signal or said second signal is issued by said means;
• and
• a single, row address decoder, operatively coupled to said row driver, for selectively receiving said first and second signals and for providing an input to said row driver.

A drive circuit for driving a plurality of memory cell blocks, comprising:

• a plurality of word line drivers corresponding to said memory cell blocks, said drivers for providing an information signal to word lines;
• and
• a single, row address decoder, operatively coupled to said plurality of word line drivers, for selectively receiving first and second signals and for providing an input to drive one of said word lines,
• said drivers for receiving first and second types of information based on said first and second signals provided to said single row address decoder depending on a first mode and a second mode.

A drive circuit for a semiconductor memory device, including:

• at least one main word line;
• a plurality of subword lines coupled to said at least one main word line;
• at least one redundant main word line arranged in regard to said at least one main word line;
• a plurality of redundant subword lines coupled to said at least one redundant main word line;
• a row address driver, commonly provided for and operatively coupled to said plurality of subword lines and said plurality of redundant subword lines, for providing a same output to said plurality of subword lines and said plurality of redundant subword lines;
• and
• a single row address decoder, operatively coupled to said row address driver, for selectively receiving first and second signals, and for providing an input to said row address driver.

A method of driving a plurality of memory cell arrays of a semiconductor memory device by a drive circuit, said method comprising the steps of:

• providing a single, row address decoder in said drive circuit for driving said semiconductor memory device;
• decoding, by a first logic gate unit in said row address decoder, a row address signal input thereto;
• holding, by an address latch circuit of said row address decoder, the output of said first logic gate unit in response to an address latch signal and a precharge signal inputted thereto;
• switching, by a switching circuit of the row address decoder, the output of said address latch circuit during a first operation and the row address signal during a second operation in response to a judging signal inputted thereto and having a first characteristic or a second characteristic;
• and
• producing, by a second logic gate unit of said row address decoder, row address decode signals used for said plurality of memory cell arrays by activating an output of said switching circuit in response to a row address enable signal inputted to said second logic gate unit,
• wherein a row address decode signal during said first operation is separated and held, and wherein said row address decode signal during the first operation and a row address decode signal during the second operation are provided at the same output.

A semiconductor memory device, comprising:

• a plurality of word lines;
• a plurality of redundancy-word lines arranged in regard to said plurality of word lines;
• a set of signal lines supplied with selection information;
• a first select line, operatively coupled to said plurality of word lines, supplied with a word line activating signal for activating a word line of said plurality of word lines;
• a second select line, operatively coupled to said plurality of redundancy-word lines, supplied with a redundancy-word line activating signal for activating a redundancy-word line of said plurality of redundancy-word lines;
• a first driver circuit, coupled to said set of signal lines and said first select line, for driving one of said word lines in response to said selection information when said word line activating signal takes an active level;
• and
• a second driver circuit, coupled to said set of signal lines and said second select line, for driving one of said redundancy-word lines in response to said selection information when said redundancy-word line activating signal takes an active level;
• and
• a single, row address decoder, operatively coupled to said first and second driver circuits and receiving first and second signals, for providing an input 2 1 to drive a selected one of said word lines and said redundancy-word lines.