Semiconductor memory device

A semiconductor memory device inputting and outputting data through an input/output circuit coupled to an internal data line, comprising;

• a DRAM array including a plurality of dynamic memory cells arranges in rows and columns;
• an SRAM array including a plurality of static memory cells arranged in rows and columns;
• amplifying means provided corresponding to each column of said DRAM array for amplifying a signal on the corresponding column;
• sense amplifier means provided for each column of said DRAM array for amplifying and latching a signal on the corresponding column;
• data transfer means provided at a position separate from said internal data line for transferring data between said DRAM array and said SRAM array;
• transmitting means responsive to a first address for transmitting an output from said amplifying means to said data transfer means;
• and
• control means responsive to a data transfer designation for activating said data transfer means at a timing earlier than activation of said sense amplifier means.

A semiconductor memory device comprising:

• first memory cell array having a plurality of static type memory cells;
• second memory cell array having a plurality of dynamic type memory cells
• data transfer means for transferring data between a selected static type memory cell and a selected dynamic type memory cell;
• data transfer bus line coupling the selected dynamic type memory cell to said data transfer means;
• clamping means for clamping a potential of said data transfer bus line;
• and
• control means said inhibiting the clamping operation of said clamping means in response to an instruction for transferring data from the selected static type memory cell to the selected dynamic type memory cell.

A semiconductor memory device, comprising:

• first memory cell array having a plurality of static type memory cells arranged in rows and columns, and a plurality of column lines each connecting a column of the static type memory cells;
• second memory cell array having a plurality of dynamic type memory cells;
• data transfer means for transferring data between a selected static type memory cell and a selected dynamic type memory cell;
• clamping means for clamping the potentials of said column lines;
• and
• control means for inhibiting the clamping operation of said clamping means in response to an instruction for data transfer from the selected dynamic type memory cell to the selected static type memory cell.