Semiconductor memory

A semiconductor memory comprising a plurality of memory cell arrays partially operating in accordance with a block selecting signal, each of memory cell arrays including memory cells arranged in a plurality of rows and in a plurality of columns and a first number of redundant memory cell rows, a second number of replacement row address programming circuits each storing the address of a row including a defective memory cell existing in the plurality of memory cell arrays, for generating a redundant row selection discriminating signal of an activated level when the stored address is designated by a given row address, the second number being smaller than the first number, and a plurality of row selection circuits including memory elements corresponding to a third number of replacement row address program circuits of the second number of replacement row address program circuits, the row selection circuits selecting, in accordance with the stored condition of the memory elements, the redundant row selection discriminating signal of the activated level supplied from the corresponding replacement row address programming circuit, for selecting the redundant memory cell row for the memory cell array corresponding to the selected redundant row selection discriminating signal, and putting all the memory cells in the same memory cell array.