Semidirect sensing circuit having combined read and write data bus
AssigneeLG Semicon Co., Ltd.
InventorDong Gyeun Kim
Life of this patent
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Abstract
A sensing circuit, in which a semidirect system is used for simplifying a circuit system, is disclosed. The sensing circuit includes: a data bus having a data line and a data bar line for reading operations and/or writing operations; a first transistor for controlling an indirect read operation; a second and third transistor, connected to the data lines, respectively, each also being connected to the same end of said first transistor, for selectively connecting one of the data lines to the first transistor; and a fourth transistor and a fifth transistor for selectively connecting the data bus to the bit line and the bit bar line, respectively, to control a direct writing operation.
Claims18
A semidirect sensing circuit in a DRAM comprising:
- a combined read and write data bus having plural data lines, each said data line being for both reading operations and writing operations;
- a reading operation circuit connected between a bit line and said data bus and between a bit bar line and said data bus, for performing an indirect reading operation;
- and
- a writing operation circuit, having components distinct from said reading operation circuit and connected between said bit line and said data bus and between said bit bar line and said data bus, for performing a direct writing operation.
A semidirect sensing circuit in a DRAM comprising:
- a combined read and write data bus having plural bus lines, each said bus line being used both in a reading operation as well as a writing operation;
- a first transistor for controlling said read operation;
- a second and third transistor, connected to said data lines, respectively, and each connected to the same end of said first transistor, for selectively connecting one of said data lines to said first transistor;
- a single fourth transistor for selectively connecting a first data line of said data bus to said bit bar line;
- and
- a single fifth transistor for selectively connecting a second data line of said data bus to said bit bar line.
Dependencies are inferred from the claim text.