Flash memory address decoder with novel latch structure

Abstract

A flash memory address decoder includes a plurality of voltage terminals to receive a plurality of voltages, an address terminal to receive a plurality of address signals and a procedure terminal to receive a procedure signal. A block decoder is coupled to the address terminal and configured to decode a portion of the address signals to provide a block select signal. A wordline decoder is coupled to the address terminal and configured to decode a portion of the address signals to provide a wordline select signal. A wordline selector circuit is coupled to the block decoder and the wordline decoder and configured to receive the block select signal and the wordline select signal and to activate addressed wordlines, where the wordline selector is configured to selectively activate addressed wordlines in the flash transistor array and to provide at least two different operational voltages simultaneously on different wordlines in the flash transistor array to accomplish a predetermined procedure responsive to the procedure signal. In one embodiment, a the address decoder includes a latch structure that latches addressed wordlines and provides operational voltages to the wordlines. In another embodiment, the block decoder and wordline decoder include latch structures that latch the block select signal and the wordline select signal to provide operational voltages to the wordline selector. Advantages of the invention include high accuracy and flexibility to read, erase and program the flash memory.

Dependencies are inferred from the claim text.