Non-volatile memory array that enables simultaneous read and write operations

A flash memory device, comprising:

• an array of flash memory cells;
• a set of write bit lines;
• a set of read bit lines;
• a plurality of switching elements connected to said flash memory cells, at least a first subset of said switching elements are connected to said read bit lines and selectively couple said read bit lines to said flash memory cells, at least a second subset of said switching elements are connected to said write bit lines and selectively couple said write bit lines to said flash memory cells;
• and
• a plurality of interconnection lines, each interconnection line connected to one of said flash memory cells, one switching element from said first subset and one switching element from said second subset.

A flash memory device comprising:

• a set of write bit lines;
• a set of read bit lines;
• two or more units, each unit being connected to said set of write bit lines and said set of read bit lines, each unit includes:
• a plurality of flash memory cells,
• a plurality of switching elements, each switching element connected to one of said flash memory cells and at least one of said write bit lines or one of said read bit lines so that each flash memory cell of said plurality of flash memory cells can be selectively coupled to one of said write bit lines or one of said read bit lines;
• and
• a plurality of interconnection lines, each interconnection line connected to one of said flash memory cells and two switching elements.

A flash memory device, comprising:

• a first write bit line;
• a first read bit line;
• a first selection line;
• a second selection line;
• a third selection line;
• a fourth selection line;
• a first flash memory cell;
• a second flash memory cell;
• a first pass gate connected to said first flash memory cell, said first selection line and said first write bit line so that when said first selection line is activated said first pass gate couples said first flash memory cell to said first write bit line;
• a second pass gate connected to said second flash memory cell, said second selection line and said first write bit line so that when said second selection line is activated said second pass gate couples said second flash memory cell to said first write bit line;
• a third pass gate connected to said first flash memory cell, said third selection line and said first read bit line so that when said third selection line is activated said third pass gate couples said first flash memory cell to said first read bit line;
• a fourth pass gate connected to said second flash memory cell, said fourth selection line and said first read bit line so that when said fourth selection line is activated said fourth pass gate couples said second flash memory cell to said first read bit line;
• a first interconnection line connected to said first pass gate, said third pass gate and said first memory cell;
• and
• a second interconnection line connected to said second pass gate, said fourth pass gate and said second memory cell.