Non-volatile semiconductor memory device having a back ground operation mode
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsAkiko Motoshima, Tomoshi Futatsuya, Akira Okugaki
Life of this patent
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Abstract
In a flash memory, a reading bit line and a writing bit line are provided corresponding to a respective column of memory cells. A well voltage and a voltage on a source line can be controlled for each sub-block. Accordingly, data can be read at a sub-block while data can be written/erased at another sub-block, and therefore, the capacity ratio of a back ground operation region to the main memory region can be changed as desired.
Claims5
A non-volatile semiconductor memory device having a back ground operation mode for reading data and writing/erasing data in a parallel manner, comprising:
- a plurality of memory cells arranged in rows and columns, each row being formed in a specific well;
- a word line provided corresponding to a respective row and connected to a control gate of a corresponding memory cell;
- a voltage control line provided corresponding to a respective row and connected to a first conduction node of a corresponding memory cell;
- a reading bit line provided corresponding to a respective column for performing data reading at a corresponding memory cell;
- a writing bit line provided corresponding to a respective column for performing data writing at a corresponding memory cell;
- selection means responsive to address signals for selecting a memory cell in a row for which said data reading is to be performed and a memory cell in another row for which said data writing/erasing is to be performed;
- first connection means for connecting a second conductive node of the memory cell selected by said selection means for said data reading to the corresponding reading line;
- second connection means for connecting a second conductive node of the memory cell selected by said selection means for said data writing to the corresponding writing bit line;
- and
- mode execution means for executing said back ground operation mode.
A non-volatile semiconductor memory device having a back ground operation mode for reading data and writing/erasing data in a parallel manner, comprising:
- a plurality of memory cell arrays each formed on a respective, specific well and including a plurality of memory cells arranged in rows and columns;
- a word line provided corresponding to a respective column in a respective memory cell array and connected to a control gate of a corresponding memory cell;
- a voltage control line provided corresponding to a respective row in a respective memory cell array and connected to a first conduction node of a corresponding memory cell;
- a reading bit line provided corresponding to a respective column commonly over said plurality of memory cell arrays for performing data reading at a corresponding memory cell;
- a writing bit line provided corresponding to a respective column commonly over said plurality of memory cells arrays for performing data writing at a corresponding memory cell;
- selection means responsive to address signals for selecting a memory cell in a memory cell array for which said data reading is to be performed and a memory cell in another memory cell array for which said data writing/erasing is to be performed;
- first connection means for connecting a second conductive node of the memory cell selected by said selection means for said data reading to the corresponding reading bit line;
- second connection means for connecting a second conductive node of the memory cell selected by said selection means for said data writing to the corresponding writing bit line;
- and
- mode execution means for executing said back ground operation mode.
Dependencies are inferred from the claim text.