Ram cell capable of storing 3 logic states

A memory cell which comprises:

• an impedance transistor having a first terminal, a second terminal, and a gate, said gate is configured to store a charge indicative of a data magnitude;
• a flip-flop having an input node, and an output node, wherein said output node is coupled to said first terminal of said impedance transistor, said flip-flop is configured to hold a state indicative of a data sign;
• a read transistor coupled to said second terminal of said impedance transistor, said read transistor configured to conduct a current through said impedance transistor when a read signal is asserted;
• a first write transistor coupled to said input node, said first write transistor configured to set the state of said flip-flop when a write signal is asserted;
• and
• a second write transistor coupled to said gate of said impedance transistor, said second write transistor configured to store said charge on said gate when said write signal is asserted.