Ferroelectric memory using non-remnant reference circuit

An integrated circuit memory comprising:

• an array of ferroelectric memory cells;
• a sense amplifier to sense and amplify data stored on the ferroelectric memory cells;
• first and second bit lines for coupling the ferroelectric memory cells to the sense amplifier;
• and
• reference circuitry selectively coupled to either the first or second bit line, the reference circuitry having a non-remnant capacitor circuit for providing a reference voltage, a capacitance of the non-remnant capacitor circuit can be adjusted using an electronic key.

A method of reading a ferroelectric memory comprising a plurality of ferroelectric memory cells, first and second bit lines, and a sense amplifier, the method comprising the steps of:

• equilibrating the first and second bit lines to a ground potential;
• selectively coupling one of the ferroelectric memory cells to the sense amplifier via the first bit line;
• raising a voltage of a plate line of the one of the ferroelectric memory cells to extract data stored in the ferroelectric memory cells;
• producing a positive reference voltage using a non-remnant capacitor;
• and
• electrically coupling the reference voltage to the sense amplifier via the second bit line.

An integrated circuit memory comprising:

• an array of ferroelectric memory cells;
• a sense amplifier to sense and amplify data stored on the ferroelectric memory cells;
• first and second bit lines for coupling the ferroelectric memory cells to the sense amplifier;
• and
• reference circuitry selectively coupled to either the first or second bit line, the reference circuitry having a non-remnant capacitor circuit for providing a reference voltage, the non-remnant capacitor circuit is comprised of a conductor line having a line capacitance, and a plurality of capacitors selectively coupled to the conductor line via access devices, wherein a capacitance of each of the first and second bit lines is an order of magnitude greater than a capacitance of the reference circuitry.

An integrated circuit memory comprising:

• a sense amplifier having first and second sensing nodes;
• a first pair of bit lines connected to the first and second sensing nodes of the sense amplifier;
• a second pair of bit lines connected to the first and second sensing nodes of the sense amplifier;
• ferroelectric memory cells coupled to the first and second pair of bit lines;
• a reference line having a capacitance;
• a plurality of capacitors coupled to the reference line through access transistors;
• and
• isolation devices connected to the reference line and the second pair of bit lines for coupling the reference line to either the first or second reference node of the sense amplifier via the second pair of bit lines, wherein a capacitance of a bit line is an order of magnitude greater than a capacitance of the plurality of capacitors.