Memory array with reduced charging current

In an integrated circuit (IC) including an array of memory cells arranged in rows and columns and including a pair of bit lines per column of memory cells, the pair of bit lines per column for carrying the data of a cell and its complement, and wherein the bit lines are disposed along a level of the IC, wherein there is a capacitance, CINT, between paired bit-lines and a capacitance, CEXT, between each one of the bit-lines of a pair and the bit lines of adjacent columns, the improvement comprising:

• spacing the bit lines such that the capacitance, CINT, between the paired bit lines is less than the capacitance, CEXT, between the paired bit lines of a column and the adjacent bit lines of adjacent columns.

In an integrated circuit (IC) including an array of memory cells arranged in rows and columns and including a pair of bit-lines per column of memory cells, the pair of bit-lines per column for carrying the data of a cell and its complement, and wherein the bit-lines are disposed along a level of the IC, wherein there is a capacitance, CINT, between each two paired bit-lines and a capacitance, CEXT, between the bit-lines of adjacent columns, and wherein the bit-lines are precharged before each read operation of the memory cells, the improvement comprising:

• means for decreasing the charging current needed to charge the bit lines of the array including spacing the bit lines so that the spacing between the paired bit lines is greater than the spacing between the bit lines of each pair and the bit lines of adjacent columns.

In an integrated circuit (IC) including an array of memory cells arranged in rows and columns and including a pair of bit-lines per column of memory cells disposed within a first level of the IC, with one bit-line of a pair for carrying the data contained in the memory cells of its associated column, and the other bit-line of a pair for carrying the complement of that data, and including master bit-lines (MBL) disposed within a second level of the IC with the master bit-lines being coupled to a predetermined number of bit-lines, and the master bit-lines being arranged in pairs with one MBL of a pair for carrying the data of one or more bit lines and the other MBL of a pair for carrying the complement of that data, and wherein there is a capacitance, MCINT, between paired master bit-lines and a capacitance, MCEXT, between the master bit-lines of a pair of master bit lines and the adjacent master bit-lines, the improvement comprising:

• spacing the master bit lines so that the capacitance, MCINT, between paired master bit-lines is less than the capacitance, MCEXT, between paired master bit-lines and the adjacent master bit-lines.