Combination propagate and generate carry lookahead gate
AssigneeAdvanced Micro Devices, Inc.
InventorEric W. Mahurin
Life of this patent
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AssigneeAdvanced Micro Devices, Inc.
InventorEric W. Mahurin
Estimating the term…
Carry lookahead adders reduce the number of logic levels required to sum two numbers. A pure carry lookahead adder, however, requires circuits with large fan-outs and fan-ins making it impractical to build for a large number of bits. Carry lookahead tree adders use a plurality of small carry lookahead adders to build a complete adder. A binary carry lookahead adder is a typical implementation of a carry lookahead tree adder. Each stage of the binary carry lookahead adder generates a propagate output and generate output from propagate and generate inputs and calculates a carry output from a carry input. A modified generate circuit is introduced which reduces the propagation delay of the generate circuit. A modified propagate circuit is introduced that ensures the inputs to the modified propagate circuit do not create a short circuit. Additionally, a combination propagate and generate circuit is introduced which reduces the number of transistors required to implement the propagate and generate circuits. Still further, a quadrature carry lookahead tree adder is discussed and a combination propagate and generate circuit for the quadrature tree adder is presented.
A combined generate and propagate circuit in a carry lookahead adder, comprising:
A combined generate and propagate circuit in a carry lookahead adder, comprising:
Dependencies are inferred from the claim text.