US 5,847,981 AGranted

Multiply and accumulate circuit

AssigneeMotorola, Inc.

InventorsBrian Todd Kelley, David Mark Johnson

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Abstract

A multiply accumulate circuit (600) includes a multiply accumulate reduction circuit (527) that generates P current accumulated operands during an iteration. P operand registers (582) are coupled to the multiply accumulate reduction circuit (527). A corresponding one of the P current accumulated operands is stored in each of the P operand registers (582) in place of one of the P partial accumulated operands in response to the iteration. Each of P feedback paths (593) couples one of P outputs of the P operand registers (582) to a corresponding one of P feedback inputs of the multiply accumulate reduction circuit (527). An adder (561) that is coupled to the P outputs through isolation circuits (570) generates an output (551) in N iterations that is a sum of N products, each being a product of one of a series of N multipliers and one of a series of N multiplicands.

Claims20

Dependent claims

A multiply accumulate (MAC) circuit that generates a total value which is a multiply accumulate result of N multiply operations of a series of N multipliers and a corresponding series of N multiplicands, comprising:

a multiply accumulate reduction circuit that generates a current accumulated sum and a current accumulated carry from a multiplier, a multiplicand, a partial accumulated sum coupled to a sum feedback input thereof, and a partial accumulated carry coupled to a carry feedback input thereof;
a sum register, coupled to the multiply accumulate reduction circuit, within which the current accumulated sum is stored in place of the partial accumulated sum in response to an iteration, and wherein the sum register generates at a sum output a new partial accumulated sum equal to the current accumulated sum stored therein;
a sum feedback path that couples the new partial accumulated sum from the sum output to the sum feedback input;
a carry register, coupled to the multiply accumulate reduction circuit, within which the current accumulated carry is stored in place of the partial accumulated carry in response to the iteration, and wherein the carry register then generates as a carry output a new partial accumulated carry equal to the current accumulated carry stored therein;
a carry feedback path that couples the new partial accumulated carry from the carry output to the carry feedback input;
an adder that generates the total value from a final sum and a final carry;
and
two operand isolation circuits that couple constant values to the adder during iterations other than a last iteration, and couple the final sum and final carry to the adder during the last iteration.

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a multiply accumulate reduction circuit that generates P current accumulated operands from a multiplier, a multiplicand, and P partial accumulated operands, wherein the P partial accumulated operands are coupled to P operand feedback inputs thereof;
P operand registers, coupled to the multiply accumulate reduction circuit, which store the P current accumulated operands in place of corresponding ones of the P partial accumulated operands in response to an iteration, and wherein the P operand registers generate at P outputs P new partial accumulated operands equal to the P current accumulated operands stored therein;
P feedback paths that couple the P new partial accumulated operands to the P operand feedback inputs;
an adder that generates the total value from P final operands;
and
P operand isolation circuits that couple P constant values to the adder during iterations other than a last iteration, and couple the P final operands to the adder during the last iteration, wherein
R, D, and N are natural numbers, P is a natural number greater than 2, and K is a natural number or 0.

4 more elements

Dependencies are inferred from the claim text.