Processor and control method for performing proper saturation operation
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsSatoshi Ogura, Shinya Miyaji, Nobuo Higaki, Masato Suzuki
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Abstract
A processor including an arithmetic operation circuit and a saturation operation correction circuit both of which are connected in parallel to a register and a data bus and are activated by respective operation instructions. The saturation operation correction circuit judges whether an output from a register file exceeds either of a predetermined upper-most value and a predetermined lower-most value, and selectively outputs one of an operation result, the upper-most value, and the lower-most value.
Claims16
A processor for sequentially executing instructions in synchronization with a clock signal showing a cycle of time period t1, the processor comprising:
- a first bus;
- a second bus;
- a third bus;
- a decoder for decoding an instruction which is either of an arithmetic operation instruction and a saturation operation instruction, and outputting a value used as an operand of the decoded instruction to the first bus and/or the second bus;
- an arithmetic operation unit, including an input port connected to the first bus and the second bus and an output port connected to the second bus and the third bus, for fetching the value output by the decoder through the input port when the decoder decodes an arithmetic operation instruction, performing an operation using the fetched value as an operand within a time period t2, and outputting an operation result to the second bus and the third bus through the output port;
- and
- a saturation operation unit, including an input port connected to the second bus and an output port connected to the third bus, for fetching the value output by the decoder through the input port when the decoder decodes a saturation operation instruction, rounding off the fetched value to a value in a predetermined range within a time period t3, and outputting the rounded-off value to the third bus through the output port, wherein
- the time periods t1, t2, and t3 have relationships as shown in Formulae 1 and 2 below:
- t2.ltoreq.t1<t2+t3:
- Formula 1
- t3.ltoreq.t1<t2+t3. Formula 2
A control method for controlling a processor comprising a register file, an arithmetic operation unit, and a saturation operation unit, the control method comprising:
- a first step in which the arithmetic operation unit performs an operation using one or more values, as operands, stored in the register file and stores an operation result in the register file;
- and
- a second step in which the saturation operation unit rounds off a value stored in the register file to a value in a predetermined range, and stores the rounded-off value in the register file.
A processor comprising:
- a decoder for decoding an instruction which is either of an arithmetic operation instruction and a saturation operation instruction, and outputting a value used as an operand of the decoded instruction;
- an arithmetic operation unit arranged to receive the value output by the decoder when the decoder decodes an arithmetic operation instruction, the arithmetic operation unit performing an operation using the fetched value as an operand and outputting an operation result;
- and
- a saturation operation unit arranged to receive the value output by the decoder when the decoder decodes a saturation operation instruction, the saturation operation unit rounding off and outputting the rounded-off value.
Dependencies are inferred from the claim text.