Method of calculating a parasitic load in a semiconductor integrated circuit
AssigneeNEC Corporation
InventorKazuki Asao
Life of this patent
Estimating the term…
Abstract
A reference connection pattern is determined within a three-dimensional region together with the other connection patterns to extract data for pattern matching operation from a position of each connection pattern. An estimated parasitic load is also given as the data and is stored as a part of reference pattern data to form a data base. By the pattern matching operation between the reference pattern data and an object pattern, a coincident one of the reference pattern data is determined as a practical parasitic load. Thus, the estimated parasitic load included in the reference pattern data is detected as the practical parasitic load in the object pattern.
Claims8
A parasitic load calculating method of calculating a parasitic load in layout data or symbolic data, comprising the steps of:
- preliminarily preparing a reference model including reference pattern data composed of reference layout pattern data and an estimated parasitic load, said reference layout pattern data being based on one or more connection patterns of a three-dimensional region, said estimated parasitic load being based on a parasitic load of said three-dimensional region for both overlapping and non-overlapping ones of said one or more connection patterns;
- and
- carrying out a three-dimensional pattern matching operation between said reference layout pattern data and layout pattern data represented by said layout data or said symbolic data to thereby calculate said parasitic load based on said estimated parasitic load.
A reference pattern data preparing method, comprising:
- defining a particular connection pattern as a reference connection pattern;
- preliminarily determining a three-dimensional region containing said reference connection pattern, wherein any other connection patterns included in said three-dimensional region define peripheral connection patterns;
- and
- preparing reference pattern data based on the layout of said reference connection pattern, said peripheral connection patterns, and a substrate within said three-dimensional region, wherein said reference pattern data includes information pertaining to a relation between said reference connection pattern and at least one oblique peripheral connection pattern, wherein said oblique peripheral connection pattern is one of said peripheral connection patterns of said three-dimensional region, does not overlap vertically with said reference connection pattern, and does not overlap horizontally with said reference connection pattern.
Dependencies are inferred from the claim text.