Digital-to-analog converter interface apparatus
AssigneeSamsung Electronics Co., Ltd.
InventorWoon-Kwang Baek
Life of this patent
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Abstract
Interface circuitry is disclosed for interfacing a digital circuit to a digital-to-analog converter (DAC). The interface circuitry receives a digital input word and provides for interfacing to the DAC in any one of several formats as may be required by the particular DAC. These formats include various bit serial formats, LSB first, MSB first, etc. The interface circuitry provides clock and control signals for interfacing with the DAC in the required format.
Claims14
A digital-to-analog converter interface apparatus for interfacing a digital-to-analog converter with an equipment which requires said digital-to-analog converter, comprising:
- data input means for receiving parallel digital data from said equipment in response to a data loading signal and storing the parallel digital data;
- data output means for selectively outputting data input from said data input means in response to a first and a second format control signals and a left/right signal;
- system clock generating means for generating a main clock signal for said digital-to-analog converter interface apparatus;
- bit clock generating means for dividing the frequency of the main clock signal in response to a third format control signal and inverting the frequency-divided main clock signal;
- control clock generating means for dividing the frequency-divided main clock signal and generating a first through a sixth control clock signals;
- word clock generating means for receiving the first through the fourth control clock signals and an inverted signal of a fourth control clock signal, generating a left-cancelling signal and a right-cancelling signal, selecting one of the left-cancelling signal and the right-cancelling signals in response to the first and the second format control signals to output the selected signal as the fourth control signal, and selecting one of the control clock signals and the inverted signal of the fourth control signal in response to the third format control signal to output the selected signal as a third control signal;
- load clock generating means for receiving said control clock signals and said frequency-divided main clock signal and outputting a second control signal and said data loading signal in response to the third format control signal;
- and
- a first OR gate for performing a logic OR operation with respect to the fourth control signal and the frequency-divided main clock signal and outputting the result as a first control signal,
- wherein the third format control signal is obtained by performing a NOR operation with respect to the second format control signal and an inverted signal of the first format control signal, and the left/right signal defines the justification of the data output from the data output means.
A method of converting a data format of a parallel digital input word to a selected format for input to a digital-to-analog converter, the method comprising the steps of:
- generating a periodic system clock signal;
- generating a bit clock signal responsive to the system clock signal;
- selectively inverting or non-inverting the bit clock signal responsive to the selected format to form a bit clock output signal;
- and
- providing the bit clock output signal to the digital-to-analog converter for clocking a serial stream of output data to the digital-to-analog converter using the selected format.
Dependencies are inferred from the claim text.