Fractional divided frequency synthesizer with phase error compensating circuit

A frequency synthesizer comprising

• a crystal oscillator,
• a fixed frequency divider for dividing the output of the crystal oscillator to output a reference frequency,
• a voltage-controlled oscillator,
• a variable frequency divider for dividing the output of the voltage-controlled oscillator at a frequency dividing ratio,
• a phase comparator for detecting and outputting the phase difference of the reference frequency and the output of the variable frequency divider,
• a loop filter for smoothing the phase difference signal, which is output from the phase comparator, as a signal output to control said voltage-controlled oscillator, and
• a frequency dividing ratio generating means for providing an integral frequency dividing ratio to and controlling said variable frequency divider,
• wherein said frequency dividing ratio generating means comprises n stages (n=1,2,3, . . . ) of integrators connected in cascade and n-1 differentiators for differentiating carry-out signals of the integrators, and composed so that a phase error generated at said variable frequency divider is obtained from an output of an adder included in an integrator in a final stage of the frequency dividing ratio generating means and a phase error compensation value is output,
• and further comprising a phase error compensating means for performing phase error compensation by varying the pulse width of a signal to be used for compensating for phase error based on the phase error compensation value which is output from said frequency dividing ratio generating means.