US 5,847,607 AGranted

High speed fully differential operational amplifier with fast settling time for switched capacitor applications

AssigneeNational Semiconductor Corporation

InventorsLaurence D. Lewicki, Ion E. Opris

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Abstract

A high speed fully differential operational amplifier with fast settling time for switched capacitor applications includes a high gain active cascode applied to the operational amplifier's input stage transistors to improve the gain, provide a higher output impedance, and thus, reduce the Miller feedback gate drain capacitance of the input stage devices. This improves the speed of the amplifier. A biasing technique is used to keep the active cascodes biased during transient overload so that settling will not be adversely affected during the recovery of the cascodes. A pair of transistors are used to feed forward a fraction of the tail current to "keep-alive" the cascode transistors. In other words, the fraction of the tail current that is fed to the source of the cascode transistors via the keep-alive transistors effectively biases the active cascodes sufficiently so that they do not turn off completely during slewing.

Claims31

Dependent claims

An apparatus including a differential amplifier with reduced switched output signal settling time, comprising:

a cascode differential amplifier configured to receive first and second input bias currents and a differential input signal and in accordance therewith provide first, second and third output bias currents and a differential output signal, wherein a sum of said first and second input bias currents equals a sum of said first, second and third output bias currents, and wherein said cascode differential amplifier comprises
a first cascode amplifier which includes a first input transistor configured to receive a first phase of said differential input signal and provide a first portion of said third output bias current and which further includes a first output transistor cascode coupled to said first input transistor and configured to receive said first input bias current and provide said first output bias current and a first phase of said differential output signal, and
a second cascode amplifier which includes a second input transistor configured to receive a second phase of said differential input signal and provide a second portion of said third output bias current and which further includes a second output transistor cascode coupled to said second input transistor and configured to receive said second input bias current and provide said second output bias current and a second phase of said differential output signal;
a first bias transistor, coupled to said first output transistor, configured to receive and conduct said first output bias current;
a second bias transistor, coupled to said second output transistor, configured to receive and conduct said second output bias current;
and
a third bias transistor, coupled to said first and second input transistors, configured to receive and conduct said third output bias current;
wherein said first and second portions of said third output bias current vary between zero and respective first and second maximum currents in accordance with said first and second phases of said differential input signal, and wherein said first and second output bias currents are respective first and second nonzero currents.

5 more elements

A differential operational amplifier comprising:

a first input transistor having a source, a gate and a drain;
a second input transistor having a source, a gate and a drain, connected via the source to the source of the first input transistor;
a first cascode transistor having a source, a gate and a drain, connected via the source to the drain of the first input transistor;
a second cascode transistor having a source, a gate and a drain, connected via the source to the drain of the second input transistor;
a tail current transistor connected between the connected sources of the first and second input transistors and ground;
a first keep-alive transistor having a source, a gate and a drain, connected via the drain to the source of the first cascode transistor to provide a bias current and capacitively coupled via the gate to the source of the first cascode transistor so as to provide common mode feedback;
and
a second keep-alive transistor having a source, a gate and a drain, connected via the drain to the source of the second cascode transistor to provide a bias current and capacitively coupled via the gate to the source of the second cascode transistor so as to provide common mode feedback.

5 more elements

A method of differentially amplifying a switching signal with reduced switched output signal settling time, comprising the steps of:

receiving and differentially amplifying in a cascode manner first and second input bias currents and a differential input signal and in accordance therewith generating first, second and third output bias currents and a differential output signal, wherein a sum of said first and second input bias currents equals a sum of said first, second and third output bias currents, by performing the steps of
receiving a first phase of said differential input signal and in accordance therewith generating a first portion of said third output bias current,
receiving said first input bias current and in accordance therewith generating, in a cascode manner with respect to said first phase of said differential input signal, said first output bias current and a first phase of said differential output signal, and
receiving a second phase of said differential input signal and in accordance therewith generating a second portion of said third output bias current,
receiving said second input bias current and in accordance therewith generating, in a cascode manner with respect to said second phase of said differential input signal, said second output bias current and a second phase of said differential output signal;
receiving and conducting said first output bias current;
receiving and conducting said second output bias current;
and receiving and conducting said third output bias current;
wherein said first and second portions of said third output bias current vary between zero and respective first and second maximum currents in accordance with said first and second phases of said differential input signal, and wherein said first and second output bias currents are respective first and second nonzero currents.

6 more elements

Dependencies are inferred from the claim text.