US 5,847,606 A · Low voltage CMOS amplifier output stage · patentgrep

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Abstract

A CMOS amplifier output stage including a complementary output MOSFET transistor pair whose channels are connected together in series between a supply voltage and a reference potential, and whose gates are driven by a complementary MOSFET level shifting transistor pair and by bias voltage and current circuitry. Preferably, the level shifting transistor pair is a diode-connected NMOS transistor and a diode-connected PMOS transistor, the bias circuitry includes a source follower which drives the source of one of the diode-connected transistors with a current determined by an input voltage, all active elements of the invention are MOSFET transistors, and the minimum supply voltage required for operation is (V.sub.GS +2V.sub.SAT), where V.sub.GS is the largest source to gate voltage of the MOSFET transistors and V.sub.SAT is the largest source to drain voltage of the MOSFET transistors during operation in the saturation region. This allows operation with a supply voltage as low as 1.8 volts with MOSFET transistors suitable for typical applications. The quiescent output current is well controlled and is determined by the device sizes of the MOSFET transistors. The invention can be implemented as part of a standard cell amplifier for any of a variety of mixed analog/digital circuits, even using high density, low voltage processes.

Claims21

Dependent claims

A CMOS amplifier output stage which produces an output voltage in response to an input voltage, comprising:

a complementary MOSFET output transistor pair having channels connected together at an output node, channel terminals for connection between a first node at a supply voltage and a second node at a reference potential, and gates;
a complementary MOSFET level shifting transistor pair having gates connected to the gates of the output transistor pair, and having channel terminals;
and
bias voltage and current circuitry connected to the gates of the output transistor pair and to the channel terminals of the level shifting transistor pair, wherein the bias voltage and current circuitry is configured to receive the input voltage and assert voltages and currents to the gates of the output transistor pair and the channel terminals of the level shifting transistor pair in response to the input voltage, so that the bias voltage and current circuitry and the level shifting transistor pair cause the complementary output transistor pair to assert the output voltage at the output node,
wherein all active components of the output transistor pair, the level shifting transistor pair, and the bias voltage and current circuitry are MOSFET transistors, the MOSFET transistors of the bias voltage and current circuitry and the level shifting transistor pair are configured to operate in saturation and not in the triode state during operation of the output stage, and the output stage is configured to require a minimum supply voltage of V.sub.GS +2V.sub.SAT, where V.sub.GS is the largest source to gate voltage drop of the MOSFET transistors during operation and V.sub.SAT is the largest source to drain voltage drop of the MOSFET transistors during operation of the output stage.

2 more elements

A CMOS amplifier output stage which produces an output voltage in response to an input voltage, comprising:

a complementary MOSFET output transistor pair having channels connected together at an output node, channel terminals for connection between a first node at a supply voltage and a second node at a reference potential and gates;
a complementary MOSFET level shifting transistor pair having gates connected to the gates of the output transistor pair, and having channel terminals;
and
bias voltage and current circuitry connected to the gates of the output transistor pair and to the channel terminals of the level shifting transistor pair, wherein the bias voltage and current circuitry is configured to receive the input voltage and assert voltages and currents to the gates of the output transistor pair and the channel terminals of the level shifting transistor pair in response to the input voltage, so that the bias voltage and current circuitry and the level shifting transistor pair cause the complementary output transistor pair to assert the output voltage at the output node,
wherein all active components of the output transistor pair, the level shifting transistor pair, and the bias voltage and current circuitry are MOSFET transistors, and the output stage requires a minimum supply voltage of V.sub.GS +2V.sub.SAT, where V.sub.GS is the largest source to gate voltage drop of the MOSFET transistors during operation and V.sub.SAT is the largest source to drain voltage drop of the MOSFET transistors during operation,
wherein the level shifting transistor pair comprises a first diode-connected PMOS transistor and a first diode-connected NMOS transistor, and wherein the bias voltage and current circuitry includes:
a second diode-connected NMOS transistor having a source connected to the second node and a drain;
a current source connected to the drain of the second diode-connected NMOS transistor;
a second diode-connected PMOS transistor having a source connected to the first node and a drain;
a current sink connected to the drain of the second diode-connected PMOS transistor;
a second current source connected between the second node and a third node;
a third current source connected between the first node and a fourth node;
a third PMOS transistor having a source connected to the fourth node, a gate connected to the drain of the second diode-connected PMOS transistor, and a drain;
and
a third NMOS transistor having a source connected to the third node, a gate connected to the drain of the second diode-connected NMOS transistor, and a drain,
wherein the first diode-connected PMOS transistor has a source connected to the fourth node and a drain connected to the drain of the third NMOS transistor, and the first diode-connected NMOS transistor has a source connected to the third node and a drain connected to the drain of the third PMOS transistor.

13 more elements

A CMOS amplifier output stage which produces an output voltage in response to an input voltage, comprising:

a complementary MOSFET output transistor pair having channels connected together at an output node at which the output voltage is asserted, channel terminals for connection between a first node at a supply voltage and a second node at a reference potential, and gates;
a complementary MOSFET level shifting transistor pair having gates connected to the gates of the output transistor pair, wherein the level shifting transistor pair comprises a first diode-connected PMOS transistor and a first diode-connected NMOS transistor;
and
bias voltage and current circuitry connected to the gates of the output transistor pair, wherein the bias voltage and current circuitry includes:
a second diode-connected NMOS transistor having a source connected to the reference potential, a drain, and a gate connected to the drain;
a current source connected to the drain of the second diode-connected NMOS transistor;
a second diode-connected PMOS transistor having a source connected to the first node, a drain, and a gate connected to the drain;
a current sink connected to the drain of the second diode-connected PMOS transistor;
a second current source connected between the second node and a third node;
a third current source connected between the first node and a fourth node;
a third PMOS transistor having a source connected to the fourth node, a gate connected to the drain of the second diode-connected PMOS transistor, and a drain;
a third NMOS transistor having a source connected to the third node, a gate connected to the drain of the second diode-connected NMOS transistor, and a drain;
and
an element coupled to receive the input voltage and configured to assert a signal indicative of the input voltage to one of the third node and the fourth node,
wherein the first diode-connected PMOS transistor has a source connected to the fourth node, a drain connected to the drain of the third NMOS transistor, and a gate connected to a first one of the gates of the output transistor pair, and
wherein the first diode-connected NMOS transistor has a source connected to the third node, a drain connected to the drain of the third PMOS transistor, and a gate connected to a second one of the gates of the output transistor pair.

13 more elements

A CMOS amplifier output stage which produces an output voltage in response to an input voltage, comprising:

a complementary MOSFET output transistor pair having channels connected together at an output node, channel terminals for connection between a first node at a supply voltage and a second node at a reference potential, and gates;
a complementary MOSFET level shifting transistor pair having gates connected to the gates of the output transistor pair, and having channel terminals;
and
bias voltage and current circuitry connected to the gates of the output transistor pair and to the channel terminals of the level shifting transistor pair, wherein the bias voltage and current circuitry is configured to receive the input voltage and assert voltages and currents to the gates of the output transistor pair and the channel terminals of the level shifting transistor pair in response to the input voltage, so that the bias voltage and current circuitry and the level shifting transistor pair cause the complementary output transistor pair to assert the output voltage at the output node,
wherein all active components of the output transistor pair, the level shifting transistor pair, and the bias voltage and current circuitry are MOSFET transistors, the MOSFET transistors of the bias voltage and current circuitry and the level shifting transistor pair are configured to operate in saturation and not in the triode state during operation of the output stage, and the output stage is configured to require a minimum supply voltage not greater than 1.8 volts.

2 more elements

A CMOS amplifier output stage which produces an output voltage in response to an input voltage, comprising:

a complementary MOSFET output transistor pair having channels connected together at an output node, channel terminals for connection between a first node at a supply voltage and a second node at a reference potential, and gates;
a complementary MOSFET level shifting transistor pair having gates connected to the gates of the output transistor pair, and having channel terminals;
and
bias voltage and current circuitry connected to the gates of the output transistor pair and to the channel terminals of the level shifting transistor pair, wherein the bias voltage and current circuitry is configured to receive the input voltage and assert voltages and currents to the gates of the output transistor pair and the channel terminals of the level shifting transistor pair in response to the input voltage, so that the bias voltage and current circuitry and the level shifting transistor pair cause the complementary output transistor pair to assert the output voltage at the output node,
wherein all active components of the output transistor pair, the level shifting transistor pair, and the bias voltage and current circuitry are MOSFET transistors, and the output stage requires a minimum supply voltage not greater than 1.8 volts, wherein the level shifting transistor pair comprises a first diode-connected PMOS transistor and a first diode-connected NMOS transistor, and wherein the bias voltage and current circuitry includes:
a second diode-connected NMOS transistor having a source connected to the reference potential and a drain;
a current source connected to the drain of the second diode-connected NMOS transistor;
a second diode-connected PMOS transistor having a source connected to the first node and a drain;
a current sink connected to the drain of the second diode-connected PMOS transistor;
a second current source connected between the second node and a third node;
a third current source connected between the first node and a fourth node;
a third PMOS transistor having a source connected to the fourth node, a gate connected to the drain of the second diode-connected PMOS transistor, and a drain;
and
a third NMOS transistor having a source connected to the third node, a gate connected to the drain of the second diode-connected NMOS transistor, and a drain,
wherein the first diode-connected PMOS transistor has a source connected to the fourth node and a drain connected to the drain of the third NMOS transistor, and the first diode-connected NMOS transistor has a source connected to the third node and a drain connected to the drain of the third PMOS transistor.

12 more elements

Dependencies are inferred from the claim text.