Switched capacitor common mode feedback circuit for differential operational amplifier and method

An operational amplifier circuit comprising in combination:

• (a) a differential operational amplifier having first and second outputs;
• and
• (b) a common mode feedback circuit including
• i. first and second common mode voltage control terminals coupled to the first and second outputs, respectively;
• ii. a first operating point control transistor having a source coupled to a first supply voltage conductor conducting a first supply voltage and a drain coupled to the first common mode voltage control terminal, and a second operating point control transistor having a source coupled to a second supply voltage conductor conducting a second supply voltage and a drain coupled to the first common mode voltage control terminal;
• iii. a third operating point control transistor having a source coupled to a first supply voltage conductor conducting a first supply voltage and a drain coupled to the second common mode voltage control terminal, and a fourth operating point control transistor having a source coupled to a second supply voltage conductor conducting a second supply voltage and a drain coupled to the first common mode voltage control terminal;
• iv. a first common mode feedback capacitor having a first terminal coupled to a gate of the first operating point control transistor and a second terminal coupled to the first common mode voltage control terminal and a first terminal of a second common mode feedback capacitor having a second terminal coupled to a gate of the second operating point control transistor;
• v. a third common mode feedback capacitor having a first terminal coupled to the gates of the first and third operating point control transistors and a second terminal coupled to the second common mode voltage control terminal and a first terminal of a fourth common mode feedback capacitor having a second terminal coupled to the gates of the second and fourth operating point control transistors;
• and
• vi. a switched capacitor circuit including first and second sampling capacitors and first, second, third, fourth and fifth switches interconnected to sample a first reference voltage and the first and second supply voltages onto the first and second sampling capacitors and then redistribute resulting charges thereon onto at least one of the first, second common mode feedback capacitors, and then sample a second reference voltage and the first and second supply voltages onto the first and second sampling capacitors and then redistribute resulting charges thereon onto at least one of the third and fourth common mode feedback capacitors,
• so as to establish and maintain the first reference voltage on the gates of the first and third operating point transistors, respectively, to cause them to produce a common mode output voltage on the first output of the differential operational amplifier, and to also establish and maintain the second reference voltage on the gates of the second and fourth operating point transistors, respectively, to cause them to produce the common mode output voltage on the second output of the differential operational amplifier.

A method of generating a common mode output voltage on first and second outputs of a differential operational amplifier by using a common mode feedback circuit including

• i. first and second common mode voltage control terminals coupled to the first and second outputs, respectively,
• ii. a first operating point control transistor having a source coupled to a first supply voltage conductor conducting a first supply voltage and a drain coupled to the first common mode voltage control terminal, and a second operating point control transistor having a source coupled to a second supply voltage conductor conducting a second supply voltage and a drain coupled to the first common mode voltage control terminal,
• iii. a third operating point control transistor having a source coupled to a first supply voltage conductor conducting a first supply voltage and a drain coupled to the second common mode voltage control terminal, and a fourth operating point control transistor having a source coupled to a second supply voltage conductor conducting a second supply voltage and a drain coupled to the first common mode voltage control terminal,
• iv. a first common mode feedback capacitor having a first terminal coupled to a gate of the first operating point control transistor and a second terminal coupled to the first common mode voltage control terminal and a first terminal of a second common mode feedback capacitor having a second terminal coupled to a gate of the second operating point control transistor, and
• v. a third common mode feedback capacitor having a first terminal coupled to the gates of the first and third operating point control transistors and a second terminal coupled to the second common mode voltage control terminal and a first terminal of a fourth common mode feedback capacitor having a second terminal coupled to the gates of the second and fourth operating point control transistors,
• the method comprising the steps of:
• (a) providing a switched capacitor circuit including first and second sampling capacitors and first, second, third, fourth and fifth switches interconnected to sample first and second reference voltages and first and second supply voltages;
• (b) operating the switched capacitor circuit to sample the first reference voltage and the first and second supply voltages onto the first and second sampling capacitors and then redistribute resulting charges thereon onto at least one of the first and second common mode feedback capacitors;
• and
• (c) operating the switched capacitor circuit to sample a second reference voltage and the first and second supply voltages onto the first and second sampling capacitors and then redistribute resulting charges thereon onto at least one of the third and fourth common mode feedback capacitors,
• so as to establish and maintain the first reference voltage on the gates of the first and third operating point transistors, respectively, to cause them to produce a common mode output voltage on the first output of the differential operational amplifier, and to also establish and maintain the second reference voltage on the gates of the second and fourth operating point transistors, respectively, to cause them to produce the common mode output voltage on the second output of the differential operational amplifier.