Semiconductor device having controllable internal potential generating circuit

Abstract

A semiconductor memory device includes a mode detection circuit for generating a mode detection signal in response to external input signals /RAS, /CAS and /WE, an internal potential generating circuit for generating and supplying to an output node an internal potential, in response to an activated potential control signal, and an internal potential control circuit for activating a potential control signal when a potential at the output node has not yet reached a predetermined potential in a case where mode detection signal indicates a mode other than the test mode, and for activating the potential control signal when the potential at the output node has not yet reached an externally supplied external reference potential in a case where the mode detection signal indicates the test mode. When external input signals are applied at a predetermined timing, a mode detection signal indicating the test mode is generated, and when the potential at the output node of the internal potential generating circuit has not yet reached the external reference potential, an internal potential is generated and supplied to the output node. Therefore, the internal potential can be controlled in accordance with the external reference potential.

Dependencies are inferred from the claim text.