Programmable multiple CCD clock synthesizer

A multiple clock synthesizer circuit for generating lower frequency clock pulses from a higher frequency clock signal, said clock synthesizer circuit comprising:

• an oscillator section for providing a train of pulses having leading and trailing edge transitions which correspond to transitions of a master clock signal;
• a first register coupled to said oscillator for dividing the train of pulses by a fixed integer to produce a plurality of first phase shifted signals corresponding in number to said fixed integer;
• a plurality of second shift registers corresponding in said number to said fixed integer and each having a clocking input coupled to a respective one of said first phase shifted signals, and producing a plurality of second phase shifted signals having leading and trailing edge transitions and having successive leading edge transitions separated from each other by time displacements corresponding to the transitions of the master clock signal;
• an output waveform generation section for combining said plurality of second phase shifted signals to generate the lower frequency clock pulses;
• wherein said first shift register and said plurality of said second shift registers are programmable to produce said first and second phase shifted signals having selectively variable pulse periods;
• and
• a load circuit for synchronizing an external load pulse with said master clock signal for initially programming said first register and said second registers.