Sense amplifier circuit in which erroneous read operation can be prevented
AssigneeNEC Corporation
InventorHiroyuki Matsubara
Life of this patent
Estimating the term…
Abstract
In a sense amplifier circuit, a CMOS inverter is connected to a power supply voltage and inverts and amplifies a voltage on a digit line connected to a selected memory cell of a memory cell section to generate a gate control signal. The first transistor is connected to the digit line and controls current flowing through the digit line in response to the gate control signal. A data of the selected memory cell is outputted from an output of the first transistor. A stabilizing section stabilizes an operation of the CMOS inverter such that a same operation of the CMOS inverter can be performed independent from change of the power supply voltage.
Claims6
A sense amplifier circuit comprising:
- a CMOS inverter connected to a power supply voltage, for inverting and amplifying a voltage on a digit line connected to a selected memory cell of a memory cell section to generate a gate control signal;
- a first transistor connected to the digit line, for controlling current flowing through the digit line in response to the gate control signal, a data of the selected memory cell being outputted from an output of the first transistor;
- a stabilizing section connected to the CMOS inverter for stabilizing an operation of the CMOS inverter such that a same operation of the CMOS inverter can be performed independent from change of the power supply voltage.
A sense amplifier circuit comprising:
- a first P-channel transistor whose source is connected to a power supply voltage, whose gate and drain are connected to an output terminal;
- a second N-channel transistor whose drain is connected to the output terminal, whose source is connected to a first node which is connected to a selected memory cell of a memory cell section, and whose gate is connected to a second node;
- a third P-channel transistor whose source is connected to the power supply voltage, whose gate is connected to a third node, and whose drain is connected to the second node;
- a fourth N-channel transistor whose drain is connected to the second node, whose gate is connected to the first node, and whose source is connected to the ground;
- and
- a stabilizing section connected to the gate of the third transistor, for stabilizing a voltage between the gate and source of the third transistor independent from change of the power supply voltage.
A sense amplifier circuit comprising:
- a first transistor connected to a digit line, for controlling current flowing through the digit line in response to a gate control signal, the digit line is connected to a memory cell section composed of memory cells;
- a second P-channel transistor whose source is connected to a power supply voltage, whose gate is connected to a first node, and whose drain is connected to a gate of the first transistor to supply the gate control signal;
- a third N-channel transistor whose drain is connected to the gate of the first transistor, whose gate is connected to the digit line, and whose source is connected to the ground;
- and
- a bias section connected to the first node, for supplying a bias to the first node such that the second transistor always operates in a saturation region regardless of change of the power supply voltage.
Dependencies are inferred from the claim text.