High speed bidirectional bus with multiplexers

A hierarchical bidirectional bus comprising:

• a plurality of bidirectional bus segments, each segment including:
• a first chain of drivers providing a chain output signal;
• a first logic gate receiving said chain output signal;
• and
• a second logic gate receiving said chain output signal, wherein said first and second logic gates propagate their respective output signals in different directions,
• wherein each first logic gate forms part of a first logic gate chain and each second logic gate forms part of a second logic gate chain;
• a third logic gate receiving a first output signal from said first logic gate chain;
• and
• a fourth logic gate receiving a second output signal from said second logic gate chain, wherein said third and fourth logic gates propagate their respective output signals in different directions, and wherein each third logic gate forms part of a third logic gate chain and each fourth logic gate forms part of a fourth logic gate chain.

A bidirectional bus including a plurality of segments, each segment comprising:

• a chain of bus drivers providing a first output signal;
• a first logic gate receiving said first output signal;
• a second logic gate receiving said first output signal,
• wherein said first and second logic gates propagate their respective output signals in different directions, wherein the first logic gates of said plurality of segments form a first logic gate chain and the second logic gates of said plurality of segments form a second logic gate chain;
• and
• means for combining the signals on said first and second logic gate chains.