Loading patent…
AssigneeVirtual Machine Works, Inc.
InventorsMichael Donald Noakes, Charles W. Selvidge, Anant Argarwal, Jonathan Babb, Matthew L. Dahl
Estimating the term…
A programmable logic circuit includes a programmable logic array which generates a plurality of output signals for output from a single port on the programmable logic circuit, and which processes a plurality of input signals received from a single port on the programmable logic circuit. The programmable logic circuit also includes multiplexing means for receiving the plurality of output signals generated by the programmable logic array and for multiplexing the plurality of output signals. An output port outputs, from the programmable logic circuit, the multiplexed plurality of output signals generated by the programmable logic array. An input port receives a multiplexed plurality of input signals, and a demultiplexing means demultiplexes the multiplexed plurality of input signals and configurably communicates the demultiplexed plurality of input signals to the programmable logic array. This demultiplexing means and the multiplexing means are each operable at a clock speed which is different from a clock speed of the programmable logic array.
A programmable logic circuit having a programmable logic array which generates a plurality of output signals for output from a single port on the programmable logic circuit, and which processes a plurality of input signals received from a single port on the programmable logic circuit, the programmable logic circuit comprising:
A method of inputting and outputting a plurality of signals from a programmable logic circuit which includes a programmable logic array that generates a plurality of output signals and that processes a plurality of input signals, the method comprising the steps of:
Dependencies are inferred from the claim text.