Back to results
US 5,847,451 AGranted
Multi-layered printed circuit board, and grid array package adopting the same
OwnerToru Ohtaki, Yasuteru Ichida +1inventors
InventorsToru Ohtaki, Yasuteru Ichida, Yasushi Takeuchi
Life of this patent
Estimating the term…
Abstract
In a multi-layered printed circuit board on which an LSI having a plurality of power supply pins and a plurality of signal pins is mounted, and a grid array package which adopts the printed circuit board, some or all of the plurality of power supply pins are connected to a power supply pattern via an inductance pattern, thereby reducing generation of radiation noise.
Claims26
A multi-layered printed circuit board comprising:
- an LSI mounted on said circuit board, sa d LSI having a plurality of power supply pins and a plurality of signal pins;
- an inductance pattern formed as a circuit pattern on said circuit board, one end of said inductance pattern being connected to at least one of the plurality of power supply pins of said LSI;
- and
- a power supply pattern formed on said circuit board, said power supply pattern being connected to the other end of said inductance pattern.
1 more element
A multi-layered printed circuit board comprising:
- an LSI mounted on said circuit board, said LSI having a plurality of power supply pins and a plurality of signal pins;
- an inductance pattern formed on a signal layer of said circuit board, one end of said inductance pattern being connected to at least one of the plurality of power supply pins of said LSI;
- a power supply pattern formed on a power supply layer of said circuit board;
- and
- a through hole for connecting said power supply pattern and the other end of said inductance pattern.
2 more elements
A multi-layered printed circuit board comprising:
- an LSI mounted on said circuit board, said LSI having a plurality of power supply pins and a plurality of ground pins;
- an inductance pattern formed on a first layer of said circuit board, one end of said inductance pattern being connected to at least one of the plurality of power supply pins of said LSI;
- a power supply pattern formed on a second supply layer of said circuit board;
- a first through hole for connecting said inductance pattern and the other end of said power supply pattern;
- a ground pattern formed on a third layer of said circuit board;
- and
- a second through hole for connecting said ground pattern and the ground pins.
4 more elements
A multi-layered printed circuit board comprising:
- an LSI mounted on said circuit board, said LSI having a plurality of signal pins;
- an inductance pattern formed as a circuit pattern on said circuit board, one end of said inductance pattern being connected to a predetermined pin of the plurality of signal pins of said LSI;
- and
- a signal line pattern formed on said circuit board, said signal line pattern being connected to the other end of said inductance pattern.
1 more element
A grid array package which adopts a multi-layered printed circuit board, comprising:
- a semiconductor chip mounted on said package, said semiconductor chip having a plurality of power supply pins and a plurality of signal pins;
- an inductance pattern formed as a circuit pattern on said package, one end of said inductance pattern being connected to at least one of the plurality of power supply pins of said semiconductor chip;
- and
- a power supply pattern formed on said package, said power supply pattern being connected to the other end of said inductance pattern.
1 more element
A grid array package comprising:
- a semiconductor chip mounted on a package board, said semiconductor chip having a plurality of signal pins;
- an inductance pattern formed as a circuit pattern on said package board, one end of said inductance pattern being connected to a predetermined pin of the plurality of signal pins of said semiconductor chip;
- and
- a signal line pattern formed on said package board, said signal line pattern being connected to the other end of said inductance pattern.
1 more element
A grid array package comprising:
- a semiconductor chip mounted on a first layer of a package board, said semiconductor chip having a plurality of power supply pins and a plurality of signal pins;
- an inductance pattern formed on a second layer of said package board, one end of said inductance pattern being connected to at least one of the plurality of power supply pins of said semiconductor chip;
- a power supply pattern formed on the second layer of said package board, said power supply pattern being connected to one end of said inductance pattern;
- and
- a through hole for connecting the other end of said power supply pattern and at least one of the plurality of power supply pins.
2 more elements
Dependencies are inferred from the claim text.