Structure for read-only-memory

A read-only-memory comprising:

• a set of word lines, spaced apart and parallel to each other;
• a set of bit lines, spaced apart and parallel to each other, being orthogonal to and separated from the set of word lines, the projected intersection of each word line and each bit line defining a memory cell;
• and
• a set of data resistors, arranged to interconnect a word line to a bit line at passive device cell sites which are predetermined by a memory algorithm;
• wherein each of the data resistors at a cell site has a conductance selected from a set of values adapted to provide multi-level data depths at each cell site which is occupied by a data resistor.

A structure for a read-only-memory comprising:

• a substrate having a set of first level word electrodes, a set of second level word electrodes, a set of first level bit electrodes, and a set of second level bit electrodes;
• a bottom insulator supported in part by the substrate and supported in part by the sets of first level word electrodes, second level word electrodes, first level bit electrodes, and second level bit electrodes, defining a series of apertures over each set of said electrodes;
• a set of first word lines, spaced apart and parallel to each other;
• a first set of conductive posts interconnecting each first word line to a first level word electrode, being adapted to fit within the apertures over the first level word electrodes;
• a first level insulator, supported in part by the set of first word lines and supported in part by the bottom insulator, defining a series of apertures over the sets of second level word electrodes, second level bit electrodes, and first level bit electrodes, and defining a first series of data apertures over the first level word lines at cell sites which are predetermined by a memory algorithm;
• a first set of data resistors, being restrained by the first series of data apertures, adapted to contact the first word lines;
• a set of first bit lines, spaced apart and parallel to each other, being orthogonal to the set of first word lines, being supported in part by the first insulator and supported in part by the first set of data resistors to which the bit lines make contact;
• a second set of conductive posts interconnecting each first bit line to a first level bit electrode, being adapted to fit within the apertures over the first level bit electrodes;
• a layer insulator, supported in part by the first set of bit lines and supported in part by the first insulator, defining a series of apertures over the second level word electrodes and the second level bit electrodes;
• a set of second word lines, spaced apart and parallel to each other;
• a second insulator, supported in part by the set of second word lines and supported in part by the layer insulator, defining a series of apertures over the second level bit electrodes and defining a second series of data apertures over the second set of word lines at cell sites which are determined by a memory algorithm;
• a second set of data resistors, being restrained by the second series of data apertures, adapted to contact the second set of word lines;
• a second set of bit lines, spaced apart and parallel to each other, being orthogonal to the set of second of word lines, supported in part by the second insulator and supported in part by the second set of data resistors to which said bit lines make contact;
• a third set of conductive posts, interconnecting each second word line to a second level word electrode, being adapted to fit within the apertures over the second word electrodes;
• and
• a fourth set of conductive posts, interconnecting each second bit line to a second level bit electrode, being adapted to fit within apertures over the second level bit electrodes;
• wherein said cell sites do not contain active devices.