US 5,847,425 A · Dense vertical programmable read only memory cell structures and processes for making them

Abstract

A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.

Claims9

Dependent claims

A method of erasing an electrically programmable and erasable memory cell formed on a semiconductor substrate with an electrically floating gate capacitively coupled with the substrate and a control gate capacitively coupled with the floating gate, comprising the steps of:

providing from a common polysilicon layer first and second spaced apart erase gates that are capacitively coupled with said floating gate and insulated from said control gate, and
holding said first erase gate and said control gate at substantially ground potential or less while holding said second erase gate at a positive erase voltage.

Dependencies are inferred from the claim text.

Facts

Application

08/341,411Filed 17 Nov 1994 · division

Priority

18 Dec 1990

Granted

8 Dec 1998

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10D 64/035
Of data-storage electrodes: comprising conductor-insulator-conductor-insulator-semiconductor structures

Family

Serial629,250Parent of this division · filed 18 Dec 1990

Serial117,219Parent of this division · filed 3 Sep 1993

US 5,343,063 AParent of this division · filed 30 Aug 1994

US 5,380,672 AParent of this division

US 5,847,425 AThis patent

From the US filing history. Foreign family members aren’t listed.

Dense vertical programmable read only memory cell structures and processes for making them

Life of this patent

Dense vertical programmable read only memory cell structures and processes for making them

Life of this patent

Abstract

Claims9