Thin film field effect transistor

A thin film field effect transistor produced according to the following steps:

• providing a bottom gate within a layer of insulating material;
• providing first and second electrically conductive source/drain blocks comprising conductively doped semiconductive material, the source/drain blocks being elevationally higher and opposingly adjacent the bottom gate, the source block being separated from the drain block by a gap which overlies at least a portion of the bottom gate;
• providing a gate insulating layer over the bottom gate, the gate insulating layer extending across at least a portion of the bottom gate overlied by the gap;
• and
• providing a thin film transistor layer over the first and second source/drain blocks and gate insulating layer, the thin film transistor layer electrically interconnecting with the first and second conductive source/drain blocks to define composite first and second source/drain regions having thicknesses greater than an intervening thin film transistor channel region.

A thin film field effect transistor produced according to the following sequential steps:

• providing a thin film transistor layer comprising first and second source/drain areas separated by an intervening thin film channel region, the thin film transistor layer having a selected thickness;
• providing a top gate insulating layer and a top gate over at least a portion of the thin film channel region;
• providing a layer of electrically conductive material over the top gate and thin film transistor layer, the electrically conductive material ultimately comprising conductively doped semiconductive material;
• patterning and etching the electrically conductive material to define first and second source/drain blocks over the respective thin film first and second source/drain areas, at least a portion of one of the blocks overlapping with conductive material of the top gate;
• and
• the first and second source/drain blocks electrically interconnecting with the respective thin film first and second source/drain areas to define composite first and second source/drain regions having thickness which is greater than the thin film layer thickness.

A thin film field effect transistor produced according to the following sequential steps:

• providing a thin film transistor layer comprising first and second source/drain areas separated by an intervening thin film channel region, the thin film transistor layer having a selected thickness;
• providing a layer of electrically conductive material over the thin film transistor layer, the electrically conductive material ultimately comprising conductively doped semiconductive material;
• patterning and etching the electrically conductive material to define first and second source/drain blocks, the first and second source/drain blocks being over the respective thin film first and second source/drain areas and electrically interconnecting with the respective thin film first and second source/drain areas to define composite first and second source/drain regions having thickness which is greater than the thin film layer thickness;
• providing a top gate insulating layer over the thin film channel region;
• providing a top gate layer over the top gate insulating layer;
• and
• patterning and etching the top gate layer to define a top gate over the thin film channel region.

A bottom gate thin film field effect transistor comprising:

• a gate;
• a gate insulator disposed over the gate;
• a thin film channel region over the gate insulator;
• a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region, the entireties of the source/drain regions extending elevationally away from the gate and terminating at respective uppermost surfaces, the uppermost surfaces being generally planar;
• and
• the first source/drain region having a first thickness, the second source/drain region having a second thickness, the thin film channel region having at least a portion with a third thickness;
• at least one of the first and second thicknesses being greater than the third thickness.

A thin film field effect transistor comprising:

• a thin film transistor layer comprising first and second source/drain areas separated by an intervening thin film channel region, the thin film transistor layer having a thickness no greater than about 350 Angstroms, at least one of the source/drain areas having a dopant concentration and a joinder region sidewall proximate the thin film channel region which defines a dopant region terminus;
• a pair of opposing source/drain blocks adjacent the thin film channel region, one of the blocks comprising a sidewall in general registered alignment with the joinder region sidewall;
• and
• at least part of an individual source/drain block of the pair of source/drain blocks being thicker than the thin film channel region thickness.

A thin film field effect transistor comprising:

• a bottom gate;
• a thin film channel region over the bottom gate and having a thickness no greater than about 350 Angstroms;
• a pair of opposing source/drain regions adjacent the thin film channel region and elevationally higher than the bottom gate, the entireties of the source/drain regions extending generally elevationally away from the gate and terminating at respective uppermost surfaces, the entireties of the uppermost surfaces being generally planar and substantially coplanar with one another;
• and
• at least part of an individual source/drain region of the pair of source/drain regions being thicker than the thin film channel region thickness.