Integrated circuit which uses a damascene process for producing staggered interconnect lines

A method for forming a multilevel interconnect structure, comprising:

• forming a first interconnect upon a semiconductor topography;
• depositing a first dielectric upon said first interconnect;
• etching through said first dielectric in select regions directly above said first interconnect to form three vias;
• depositing a plug conductor material within said three vias to form three plugs;
• depositing a second dielectric upon said first dielectric and said three plugs;
• etching through said second dielectric directly above said three plugs to form an intermediate via coplanar with and interposed between a pair of trenches;
• depositing a second conductor material within said intermediate via and within said pair of trenches to form a fourth plug within said intermediate via and a pair of second interconnects within the pair of trenches;
• and
• forming a third interconnect directly above and upon said fourth plug such that the third interconnect is laterally offset from the second interconnects.