Microstructure and single mask, single-crystal process for fabrication thereof
AssigneeCornell Research Foundation, Inc.
InventorsKevin A. Shaw, Z. Lisa Zhang, Noel C. MacDonald
Life of this patent
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Abstract
A single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independently of crystal orientation.
Claims24
A single-mask, low temperature reactive ion etching process for fabricating high aspect ratio, submicron, released single crystal microelectromechanical structures independently of crystal orientation, comprising:
- forming a mask dielectric layer on a top surface of a single crystal substrate;
- patterning said mask dielectric layer to produce a dielectric mask defining a structure of arbitrary shape to be formed in and surrounded by said substrate, said shape being independent of crystal orientation in said substrate and including at least a beam portion to be released;
- etching said substrate through the pattern defined by said dielectric mask and through said top surface to produce a corresponding continuous deep trench in said substrate around the defined structure of arbitrary shape, said structure having a top surface covered by said mask dielectric layer and having side walls substantially perpendicular to said top surface;
- forming a protective dielectric layer on said structure side walls, on the floor of said trenches, and on said dielectric mask;
- removing the protective dielectric layer from the floor of said trenches to expose said single crystal substrate while leaving said dielectric mask and said side wall protective dielectric layer substantially intact;
- undercutting said defined structure and releasing at least said beam portion of said defined structure by reactive ion etching said exposed single crystal substrate in said trenches;
- and
- thereafter coating the top and the side walls of said defined structure and surrounding substrate with a metal layer, the metal on said defined structure being electrically isolated from the metal on the surrounding substrate by said trenches.
A process for fabricating microelectromechanical structures, comprising:
- producing in a surface of a substrate a continuous trench which defines in said surface and in said substrate an island of arbitrary shape separated from the remainder of the substrate, the remainder of the substrate forming a mesa adjacent to and surrounding said island, said trench having walls on said island and on said mesa extending substantially vertically downwardly from said surface to horizontally separate the island from the mesa;
- covering said island, mesa, and vertical side walls with an electrically insulating layer;
- partially undercutting said island along the length of said vertical wall on said island to produce a continuous island undercut region along the length of said trench;
- and
- thereafter depositing on said island and mesa insulating layer an electrically conductive layer, said undercut region breaking the continuity of said conductive layer to electrically isolate the conductive layer on said island from the conductive layer on said mesa.
A reactive ion etching process for fabricating high aspect ratio single crystal microelectromechanical structures independently of crystal structure, comprising:
- producing on a surface of a single crystal substrate a mask pattern for a structure of arbitrary shape to be formed in said substrate, said shape being independent of crystal orientation in said substrate and including at least a beam portion to be released;
- producing in said substrate a continuous trench corresponding to said pattern to form said structure having said arbitrary shape, said trench having spaced, substantially vertical walls to separate said structure horizontally from a mesa portion of said substrate surrounding said structure, said trench completely surrounding said structure and having a floor extending between said walls;
- releasing at least a portion of said structure from said substrate to form a released beam portion movable with respect to said substrate;
- undercutting the remaining portion of said structure at said trench floor, providing a dielectric layer on said structure and said mesa;
- and
- after releasing and under cutting, depositing on said dielectric layer a conductive layer, said undercut portion of said structure electrically isolating the conductive layer on said structure.
The process of claim wherein 18, wherein releasing said beam portion includes etching at least a part of said beam portion to thereby reduce the size of said beam portion.
A process for fabricating a microelectromechanical structure on an integrated circuit wafer incorporating at least one electrical contact connected to the circuit, comprising:
- producing in the wafer a continuous trench having a floor and substantially vertical spaced side walls, the trench extending around a microelectromechanical structure to horizontally space the structure from a surrounding mesa, said mesa carrying the integrated circuit and contact;
- covering the structure, mesa, and vertical side walls with an electrically insulating layer;
- partially undercutting said structure and said mesa at the floor of said trench beneath said insulating layer on said vertical side walls to produce undercut regions which extend continuously along said mesa and said structure;
- opening a via through said insulating layer to expose said contact;
- and
- depositing on said insulating layer and said contact an electrically conductive layer to electrically connect said layer to said circuit, said undercut region electrically isolating said conductive layer on said structure from said conductive layer on said mesa.
Dependencies are inferred from the claim text.