Cache coherency where multiple processors may access the same data over independent access paths

Abstract

The present invention, generally speaking, provides a hardware graphics accelerator for use in a computer system having a data processor, a system bus, and a memory subsystem including both main memory and video memory. The hardware graphics accelerator includes a datapath controller connected to the system bus and to the memory subsystem for receiving data from the memory subsystem, performing an operation upon the data, and returning the data to the memory subsystem; and a memory controller connected to the system bus, to the datapath controller, and to the memory subsystem for controlling the memory subsystem such that at one time the datapath controller receives the data from the main memory and at another time the datapath controller receives the data from the video memory. In accordance with a further aspect of the invention, the hardware graphics accelerator includes circuitry for maintaining cache coherency when the system includes either a level-one cache only or both a level-one and a level-two cache.

Dependencies are inferred from the claim text.