Computer system and method for obtaining memory check points and recovering from faults using the checkpoints and cache flush operations

A computer system having a processor, a main memory, a copyback type cache memory, the computer system periodically storing contents of the processor and the cache, memory into the main memory to get a checkpoint on the main memory, and achieving a recovery from a fault by restarting from the checkpoint when a fault occurs, the computer system comprising:

• cache flush execution means for flushing the cache memory independently of normal data processing executed by the processor;
• cache flush start means for invoking the cache flush execution means;
• cache flush end detection means for detecting whether the cache flush execution means has finished flushing the cache memory;
• and
• cache flush stop means for stopping the execution of the cache flush execution means;
• wherein, in a first phase checkpoint, the processor commands the cache flush start means to invoke the cache flush execution means, the processor performing normal data processing while the cache flush execution means flushes the cache memory;
• and
• wherein, in a second phase checkpoint, which starts after a first period of processing time has elapsed since the start of the first phase checkpoint, the processor commands the cache flush stop means to stop the execution of the cache flush execution means and saves a state of the processor into the main memory and commands the cache flush start means to invoke the cache flush execution means, the processor suspending the normal data processing while the cache flush execution means flushes the cache memory waiting for termination of the cache flush execution means detected by the cache flush end.

In a computer system, a method of periodically storing contents of a processor and a cache memory into a main memory to get a checkpoint on the main memory and to recover from a fault by restarting from the checkpoint when a fault occurs, the method comprising the steps of:

• executing a first phase checkpoint step where a cache flush operation and normal data processing are performed simultaneously;
• detecting whether the first phase checkpoint step is complete;
• and
• executing a second phase checkpoint step, wherein a cache flush operation is performed and any normal data processing is suspended until completion of the second phase checkpoint step.