Virtual address write back cache with address reassignment and cache block flush

In a computer system with cache flushing comprising a central processing unit operating in accordance with a shared, multi-user operating system having multiple concurrently active contexts and a kernel;

• a main memory;
• a memory management unit, coupled to said processor and said main memory, for translating an address in virtual space into a corresponding address in physical space;
• a virtual cache data array, coupled to said central processing unit, for storing a first plurality of blocks of data;
• a virtual cache tag array, coupled to said virtual cache data array and said central processing unit, for storing a plurality of tag array elements wherein, each tag array element corresponds to a particular block of data stored in said virtual address cache data array and further includes:
• a validity bit, a modification bit, a protection bit, a write allowed bit, a plurality of virtual address field bits, and a plurality of context bits;
• cache hit logic means, coupled to said processor and said virtual cache tag array, for determining whether accesses from said central processing unit results in a cache hit or a cache miss;
• cache flush logic means, coupled to said central processing unit and said cache hit logic means, for directing the flushing of said virtual address cache data array;
• a method for selectively flushing said virtual cache data array comprising the steps of:
• said central processing unit coupling a context match flush command defined by said kernel of said shared, multi-user operating system, comprising a plurality of context identifier bits, to said cache flush logic means and said virtual cache tag array;
• responsive to said context match flush command, said cache flush logic means flushing a first block of data from said virtual cache data array in the event that:
• the protection bit in the tag array element corresponding to said first block of data is in a first predesignated state;
• and
• the plurality of context bits in the tag array element corresponding to said first block of data match said plurality of context identifier bits.