Method and apparatus for reducing the access time of a memory device by decoding a row address during a precharge period of the memory device

In a computer system having a processor and a memory device having a data bus, an address bus, and at least one control input, a method of operating the computer system comprising:

• applying a row address to the address bus of the memory device, the row address being derived from an address generated by the processor;
• applying to a control input of the memory device an externally generated control signal that transitions from a first logic level to a second logic level, the externally generated control signal derived from an externally generated control signal generated by the processor;
• in response to the transition of the externally generated control signal from the first logic level to the second logic level, decoding the row address in the memory device;
• applying to a control input of the memory device an externally generated control signal that transitions from the second logic level to the first logic level, the externally generated control signal derived from an externally generated control signal generated by the processor;
• and
• in response to the transition of the externally generated control signal from the second logic level to the first logic level, activating a row of memory cells that may correspond to the decoded row address.

In a computer system having a processor and a memory device having a data bus, an address bus, and at least one control input, a method of operating the computer system comprising:

• applying a row address to the address bus of the memory device, the row address being derived from an address generated by the processor;
• applying to a control input of the memory device an externally generated control signal that transitions from a first logic level to a second logic level, the externally generated control signal derived from an externally generated control signal generated by the processor;
• in response to the transition of the externally generated control signal from the first logic level to the second logic level, checking for the need to substitute a row of memory cells for the row of memory cells corresponding to the row address;
• and
• applying to a control input of the memory device an externally generated control signal that transitions from the second logic level to the first logic level, the externally generated control signal derived from an externally generated control signal generated by the processor;
• and
• in response to the transition of the externally generated control signal from the second logic level to the first logic level, activating the row of memory cells that needed to be substituted for a row of memory cells corresponding to the row address.

A memory device having an address bus, a data bus, and an address strobe input, the memory device comprising:

• an array of memory cells arranged in rows and columns, the array of memory cells being coupled to the address bus and the data bus;
• a row decoder coupled to the address bus and the address strobe input, the row decoder being adapted to decode a row address received on the address bus responsive to a transition of the row address strobe signal from a first value to a second value;
• and
• a wordline control circuit coupled to the row decoder and the array of memory cells, the wordline control circuit firing a row of the memory cells derived from a decoded row address responsive to a transition of the row address strobe signal from the second value to the first value.

A memory device having an address bus, a data bus, and an address strobe input, the memory device comprising:

• an array of memory cells arranged in rows and columns, the array of memory cells being coupled to the address bus and the data bus;
• a row decoder coupled to the address bus and the address strobe input, the row decoder being adapted to decode a row address received on the address bus;
• a redundant row checker coupled to the row decoder, the redundant row checker adapted to determine if the row of memory cells corresponding to the decoded row address is defective responsive to a transition of the row address strobe signal from a first value to a second value;
• and
• a wordline control circuit coupled to the row decoder, the redundant row checker and the array of memory cells, the wordline control circuit firing a row of the memory cells responsive to a transition of the row address strobe signal from the second value to the first value, the fired row corresponding to the decoded row address if the row of memory cells corresponding to the decoded row address is not defective, the fired row being a redundant row of memory cells if the row of memory cells corresponding to the decoded row address is defective.

A computer system, comprising:

• an input device;
• an output device;
• a processor coupled to the input device and the output device;
• and
• a memory device coupled to the processor, the memory device having an address bus, a data bus, and an address strobe input, the memory device comprising:
• an array of memory cells arranged in rows and columns, the array of memory cells being coupled to the address bus and the data bus;
• a row decoder coupled to the address bus and the address strobe input, the row decoder being adapted to decode a row address generated by the processor and received on the address bus responsive to a transition by of the row address strobe signal from a first value to a second value;
• and
• a wordline control circuit coupled to the row decoder and the array of memory cells, the wordline control circuit firing a row of the memory cells that may correspond to a decoded row address responsive to a transition of the row address strobe signal from the second value to the first value.

A computer system, comprising:

• an input device;
• an output device;
• a processor coupled to the input device and the output device;
• and
• a memory device coupled to the processor, the memory device having an address bus, a data bus, and an address strobe input, the memory device comprising:
• a row decoder coupled to the address bus and the address strobe input, the row decoder being adapted to decode a row address generated by the processor and received on the address bus;
• a redundant row checker coupled to the row decoder, the redundant row checker adapted to determine if the row of memory cells corresponding to the decoded row address is defective responsive to a transition by of the row address strobe signal from a first value to a second value;
• and
• a wordline control circuit coupled to the row decoder, the redundant row checker and the array of memory cells, the wordline control circuit firing a row of the memory cells responsive to a transition of the row address strobe signal from the second value to the first value, the fired row corresponding to the decoded row address if the row of memory cells corresponding to the decoded row address is not defective, the fired row being a redundant row of memory cells if the row of memory cells corresponding to the decoded row address is defective.

A computer system having a processor, a memory device having an address bus, a data bus and at least one control input, and a program storage device storing instructions, that, when executed by the processor, performs the steps of

• applying a row address to the address bus of the memory device;
• applying to a control input of the memory device an externally generated control signal that transitions from a first logic level to a second logic level;
• in response to the transition of the externally generated control signal from the first logic level to the second logic level, decoding the row address in the memory device;
• applying to a control input of the memory device an externally generated control signal that transitions from the second logic level to the first logic level;
• and
• in response to the transition of the externally generated control signal from the second logic level to the first logic level, activating a row of memory cells that may correspond to the decoded row address.

A computer system having a processor, a memory device having an address bus, a data bus and at least one control input, and a program storage device storing instructions, that, when executed by the processor, performs the steps of

• applying a row address to the address bus of the memory device;
• applying to a control input of the memory device an externally generated control signal that transitions from a first logic level to a second logic level;
• in response to the transition of the externally generated control signal from the first logic level to the second logic level, checking for the need to substitute a row of memory cells for the row of memory cells corresponding to the row address;
• applying to a control input of the memory device an externally generated control signal that transitions from the second logic level to the first logic level;
• and
• in response to the transition of the externally generated control signal from the second logic level to the first logic level, activating the row of memory cells that needed to be substituted for a row of memory cells corresponding to the row address.