System for accessing dynamic random access memory where the logic/control circuit temporarily stops upon word line switching

A memory access system comprising:

• a logic/control circuit;
• a memory;
• an address bus connecting the logic/control circuit and the memory;
• and
• an address transition detector circuit provided on address lines constituting the address bus;
• said address transition detector circuit detecting a memory access signal requesting memory access involving word line switching in said memory out of memory access signals transmitted from said logic/control circuit to said memory through the address lines and outputting a detection signal, and
• said logic/control circuit receiving input of a detection signal from said address transition detector circuit to temporarily stop its operation until the memory access is complete by achieving a waiting state only at a time when an address transition with the word line switching occurs at a random memory access of the memory.