System and methods for performing cache latency diagnostics in scalable parallel processing architectures including calculating CPU idle time and counting number of cache misses
AssigneeHewlett-Packard Company
InventorGary S. Brooks
Life of this patent
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Abstract
An integrated diagnostics system within a processing system for monitoring and identifying performance problems within the processing system. The processing system including at least one processor and at least one memory unit, wherein the processor is operable to read one or more addressable memory locations within the memory unit. The integrated diagnostics system including an integrated monitor for counting cache misses and idle time suffered by the processor waiting to read a first addressable memory location within the memory unit.
Claims19
A diagnostics system for use in a parallel processing system, said parallel processing system including a plurality of processors and a plurality of memory units, said plurality of processors operable to read one or more addressable memory locations within said plurality of memory units, said diagnostics system comprising:
- a first monitor for counting cache misses suffered by one or more of said plurality of processors waiting to access said plurality of addressable memory units, wherein said cache misses occur at both local and remote addressable memory units;
- a second monitor, integrated with said first monitor, for counting idle time suffered by one or more of said plurality of processors waiting to access said plurality of addressable memory units;
- means for reporting an amount of cache misses counted by the first monitor to a user of the diagnostics system;
- and
- means for reporting an amount of idle time counted by the second monitor to a user of the diagnostics system;
- wherein each memory of said plurality of memory units is associated with a particular processor of said plurality of processors, said particular processor is operable to access memory units associated with other processors of the plurality of processors.
A diagnostic system for determining performance metrics of an application executing on a parallel processing system, said parallel processing system including a plurality of processors and a plurality of memories, each memory of said plurality of memories associated with a particular processor of said plurality of processor, said diagnostic system comprising:
- means for instrumenting a code region of said application;
- and
- means for monitoring performance metrics for said instrumented code region, said means for monitoring comprising:
- first means for tracking memory cache misses incurred by at least one processor of said plurality of processors in accessing said plurality of memories, wherein said memory cache misses occur at both local and remote memories;
- and
- second means for tracking idle time incurred by said one processor from waiting to access said plurality of memories;
- wherein said mean for monitoring determines said idle time by gating a clock signal of said one processor into a counter, and determines cache misses by causing a control signal to increment said counter.
A diagnostics system for use in a parallel processing system, said parallel processing system including a plurality of processors and a plurality of memory units, said plurality of processors operable to read one or more addressable memory locations within said plurality of memory units, said diagnostics system comprising:
- a first monitor for tracking cache misses incurred by at least one processor of said plurality of processors in accessing said plurality of addressable memory units, wherein said cache misses occur at both local and remote addressable memory units;
- and
- a second monitor, integrated with said first monitor, for tracking idle time incurred by said one processor from waiting to access said plurality of addressable memory units;
- means for reporting an amount of cache misses tracked by the first monitor;
- and
- means for reporting an amount of idle time tracked by the second monitor;
- wherein each memory of said plurality of memories is associated with a particular processor of said plurality of processors, said particular processor is operable to access memories associated with other processors of the plurality of processors.
A method of determining performance metrics in a parallel processing system having a plurality of processors and a plurality of memories, each memory of said plurality of memories associated with a particular one of said plurality of processors, said plurality of processors operable to read one or more addressable memory locations within said plurality of memories, comprising the steps of:
- tracking cache misses incurred by at least one processor of said plurality of processors in accessing said plurality of addressable memory units, wherein said cache misses occur at both local and remote addressable memory units;
- and
- tracking idle time incurred by said one processor from waiting to access said plurality of addressable memory units;
- wherein said step for tracking idle time tracks said idle time for (a) a particular code region of an application, and (b) a particular thread of and application executing on said parallel processing.
Dependencies are inferred from the claim text.