Cache memory system with reduced tag memory power consumption

A cache memory system comprising:

• an address register for storing a tag address and an index address of data to be accessed;
• data memories of n-ways ("n" is an integer which is not less than two) for storing data corresponding to said index address;
• tag memories of n-ways corresponding to said data memories for storing tag addresses relating to said data stored in said data memories;
• n-tag comparators corresponding to said tag memories of n-ways, for comparing a tag address stored in said tag memories of n-ways with said tag address stored in said address register, and for determining whether a cache hit has occurred, where these tag addresses are the same, or a cache miss has occurred, where these tag addresses are different;
• a reference frequency information register for storing information indicating the way of said tag memory which has resulted in said cache hit;
• an access control circuit for selecting one of said tag memories of n-ways and one of said comparators corresponding to said selected tag memory based on said information from said reference frequency information register, for operating only said selected tag memory and the selected tag comparator, and for controlling a comparison operation between said tag address stored in said address register and a tag address in said selected tag memory, executed by said selected tag comparator, and when said comparison operation between said tag address stored in said address register and said tag address in said selected tag memory results in a cache miss, said tag memories and said tag comparators except for said selected tag memory and said selected tag comparator are operated thereafter;
• wherein n is not less than three in said n-way tag memories and said n-way data memories, and said reference frequency information register is a Most Recently Used (MRU) bit register for storing information relating to the way of said tag memory corresponding to said data memory which was referred to recently in a reference operation for said tag address;
• and
• further comprising a reference mode control signal generation means for generating a reference mode control signal to control operation of said access control circuit, and wherein said access control circuit receives said reference mode control signal and said access control circuit switches between a first reference operation mode where one of said tag memories and one of said tag comparators are executed based on said information from said MRU bit register and a second reference operation mode where all of said tag memories and all of said tag comparators are executed at the same time.