Wrapped-line cache for microprocessor system

A cache for enhancing the performance of a microprocessor system including a microprocessor and main memory, said main memory storing information in the form of binary words at respective addresses of said main memory, said main memory transmitting the word stored at an address in response to a reception of that address, each of said addresses having a line-address segment and an r-bit word-position segment, each of said line-address segments including a respective tag segment, said microprocessor transmitting a requested read address, the line-address segment of said requested address defining a requested line address, the tag segment of said requested address defining a requested tag, the word-position segment of said requested address defining a requested word-position index, said cache comprising:

• cache storage for temporarily storing those of said words that are transmitted from said main memory to said microprocessor, said cache storage having plural storage locations including a target storage location, each of said storage locations having
• a tag section for storing a tag that identifies a respective line address,
• a string-boundary section for storing an r-bit string-boundary indicator, and
• a line section for storing a string of said words, each line section having 2.sup.r word positions, each of said word positions of a line section having a respective r-bit word-position index,
• said cache storage being coupled to said microprocessor for transmitting words stored in said cache storage for processing by said microprocessor, said cache storage being coupled to said main memory for receiving words therefrom;
• match logic for making a hit-or-miss determination when said requested address is received, said match logic determining from said requested address a requested word that is the word stored at said requested address in said main memory, a hit determination indicating that said requested word is in said cache storage, said match logic causing said requested word to be transmitted from said cache storage for processing by said microprocessor in the event of a hit determination, a miss determination indicating that said requested word is not in said cache storage, said match logic storing said requested tag at the tag section of said target storage location in the event of a miss determination, said match logic storing the requested word-position index at the string-boundary section of said target storage location in the event of a miss determination, said match logic making said hit-or-miss determination as a function of the tags and the string-boundary indicators at said storage locations, said match logic being coupled to said cache storage for making said match determination and for storing said requested tag and said requested word position index therein;
• and
• an address generator for transmitting addresses to said main memory in the event of a miss determination, said address generator transmitting said requested address and 2.sup.r -1 successor addresses to said main memory, said address generator causing said requested word and the words stored at said successor addresses to be respectively stored at the word positions of said target storage location corresponding to the word-position segments of their respective main-memory addresses, said address generator being coupled to said match logic for receiving said miss determination, said address generator being coupled to said main memory for transmitting addresses thereto, said address generator being coupled to said cache storage for selecting said target storage location and word positions therein for storage of words received from said main memory.