Auxiliary register file accessing technique

A method for programming a processor, said processor carrying out designated operations on at least one operand, after retrieving said at least one operand from one or more registers, and writing a result in a destination register, addresses of said at least one operand in said one or more registers and said destination register being identified by at least two N-bit fields in an operation code format, said method comprising:

• providing in said operation code format a first address field, having N bits, containing a first address of a first storage location within a register file, said register file having up to 2.sup.N addressable locations;
• providing in said operation code format a second address field, having N bits, containing a second address of a second storage location within said register file;
• providing in said operation code format one or more register file selection bits outside of said first address field and said second address field for designating one of a plurality of register files as a selected register file for said first address and said second address, each register file in said plurality of register files having up to 2.sup.N addressable locations;
• and
• providing an instruction in said operation code format for causing said processor to apply said first address and said second address to said selected register file to read said at least one operand from said selected register file and write said result into said selected register file.

A processor comprising:

• a plurality of functional units, each functional unit for carrying out a set of instructions on one or more operands and storing a result of an operation in a register;
• a plurality of register files, each register file having up to 2.sup.N addressable locations;
• an input port receiving an instruction in an operation code format, said instruction including at least one operand address field containing a first address having N bits designating an address of a first storage location within a register file, said instruction also including a designation address field containing a second address having N bits designating a second storage location for a result of an operation carried out by a designated functional unit, said instruction also containing one or more register file selection bits outside of said at least one operand address field and said destination address field for designating one of a plurality of register files as a selected register file for said first address and said second address, each register file in said plurality register files having up to 2.sup.N addressable locations;
• and
• a controller receiving said instruction and selecting one of said plurality of register files as a selected register file based on said one or more register file selection bits, said controller applying said first address to said selected register file to read an operand from said selected register file to apply said operand to a designated functional unit.