Method and apparatus for calibrating static timing analyzer to path delay measurements

An apparatus for calibrating a circuit analyzer, comprising:

• means for determining a plurality of initial technology parameters characterizing a circuit according to a timing model of said circuit;
• means for expressing a delay along an entire logic path of said circuit as a function of said technology parameters;
• means for determining a set of circuit paths having fixed topology, device sizes, and wire capacitances;
• and
• a processor including means for optimizing said technology parameters to minimize a plurality of errors over said set of circuit paths to obtain optimized parameters for use in said timing model.

A circuit analyzer for generating a graphic representation of a predicted performance of a circuit, the circuit analyzer comprising:

• an input device for inputting a plurality of circuit parameters representing said circuit;
• memory and stored programs for receiving and storing said circuit parameters;
• a processor that is controlled by said stored programs and accesses said circuit parameters such that said processor:
• expresses a delay along an entire logic path of said circuit as a function of said circuit parameters,
• determines a set of circuit paths having fixed topology, device sizes, and wire capacitances,
• determines said circuit parameters to predict the performance of the circuit, and
• determines optimum circuit parameters to minimize a plurality of errors over said set of circuit paths to obtain optimized parameters for use in said processing means;
• and
• an output device that generates a graphic representation from said processed circuit parameters.