Operation unit and method for controlling processing speed of the same

Abstract

An operation unit includes at least one processing circuit, a completion detection circuit, and a synchronous clock generator. The detection circuit is connected to the processing circuits, and detect the completion of the operations carried out by the processing circuit. The synchronous clock generator generates a clock signal of the operation unit according to the speed of the processing circuit. If the unit includes plural processing circuits, detection circuits are connected to the processing circuits respectively. And a synthesis unit is connected to the detection circuits for receiving completion signals and prepares a general monitor flag to determine the slowest speed in the plural processing circuits. The clock signal is generated according to the slowest speed. Even if the operation speeds of LSIs scatters due to manufacturing variations, clock frequencies proper for a given LSI are dynamically and flexibly set so that every LSI may demonstrate its maximum performance.

Dependencies are inferred from the claim text.